Bridging the gap between packages and chips: 10mm super connect technology*
11/01/2000
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*This story was translated for SST from the June 2000 issue of Nikkei Microdevices, our partner in Japan.
There's fast-growing interest in Japan in the potential of 5-15mm technology, that long-ignored middle region between packages and semiconductors.
 Figure 1. Super connect technology bridges the gap between packages and chips. |
Advocates think this technology, dubbed "super connect," may be just what's needed to break through the encroaching limitations of current technology, and to make a new generation of chips and packages that are faster, cheaper, and less power-hungry. The wide-open new field presents opportunities not only to chip and package makers, but also to the materials and equipment suppliers who first come up with the new products to fill this void.
While semiconductor engineers make 0.1mm transistors and 1mm interconnects, and package engineers deal with geometries of 100mm to 1mm, no one has paid much attention to the 5-15mm area in between (Fig. 1). But now makers of wafer-scale packages, and their material and equipment suppliers, are working out the technology for producing patterns on this new scale between chips and packages, a technology that may be extended on the one hand to make chips with relatively huge 10mm connections between sections, and on the other hand to make high-density module packages with relatively tiny 10mm connections between chips.
 Figure 2. Super connect technology has the potential to significantly improve chip performance by a) improving speed; b) cutting costs; and c) cutting power consumption. |
This new approach is attracting attention now because the industry is starting to run up against barriers to improving chip performance. It's getting to the point where simply reducing pattern size may no longer be enough to increase speed and bring down cost. It's getting hard to get speed up above 2-3GHz, and especially hard to increase the speed of the interconnects within the chip, and of the signal transmission between the chip and the motherboard. Power consumption is increasingly becoming a problem, as even this generation of power-hungry chips demands big heat sinks and fans. And some system chips are paradoxically getting more expensive as they get smaller.
Super connect technology has the potential to solve these problems (Fig. 2). Giant interconnects between some sections of a chip can increase its speed (Fig. 3a). While finer patterns reduce the transistor gate delay, the finer lines also increase resistance and interconnect delay. But increasing the size of the interconnect from 1 x 1 x 1mm to 10 x 10 x 10mm cuts its resistance to 1/100, and reduces its delay to 1/1000 that of the smaller version. And giant interconnects can reduce power consumption by reducing the number of interconnect layers, which increase capacitance and consume power. Instead, the chip can be divided into separate functional sections, each with fewer, shorter connections, the sections then joined by giant interconnects. This can reportedly reduce power consumption by 60-70%.
Super connect technology may also decrease costs by allowing chips made with different processes to be joined in a module with 10mm connections for system-chip performance. (Fig. 3b).
This whole new area of geometries between chips and packages presents new business opportunities for companies that invent technologies to fill the void. Vertically integrated companies with in-house technology for both chips and packages may have the advantage, but even some of these will have to make changes to get their separate divisions to talk to each other. Equipment and materials suppliers are scrambling to come up with faster, simpler versions of their semiconductor products, or higher-precision versions of their packaging products, or better yet, some entirely new approach.
Key to both 10mm chip interconnects and package connections will be similar thick film technology (Fig. 3a, b). Since package industry metal-printing isn't high-enough quality for 10mm metal layers, and IC-industry sputtering and CVD are too slow and expensive, the best choice looks to be new metal coating processes like those promoted by Fujikura Ltd. and Vacuum Metallurgical Co. Ltd. For the insulating layers, CVD and spin coating are expensive, so producers may attach dry film insulation instead. Exposure will probably use thick film resist, so the lithography equipment will have to have high depth of focus. For etching, producers would like some process that combines the speed of wet etching with the precision of dry etching, which may emerge from new technologies being developed by the micromachining world. Improved CMP will be needed to polish the wider circuits without dishing. Package makers will also need new technologies to etch high-aspect vias, and to implant them with metal. They will also need to use thinner chips, and will need to find ways of handling these chips without damage, and ways to align them precisely in stacks. — Masahide Kimura, Nikkei Microdevices
Case Study 1: Bigger interconnects may bring big gains in chip performance
Making better semiconductors has long been a matter of making ever better transistors, and ever finer circuit lines. But the major improvements in performance over the next decade are going to have to come not from the transistors, but from the interconnects. And one major step will be making some of these interconnects larger instead of smaller, using giant 10mm connections at key places on the chip.
The interconnects now largely determine the complexity of a chip's design, consume most of its power, produce most of its delay time, and account for most of its production costs. The increasing number of interconnect layers, as the standard moves from six now to eight or ten in the next decade, makes design more complex. The more layers of interconnects in a CMOS chip, the higher the proportion of total power consumed by the interconnects. All these layers also mean that, from the 0.25mm generation on, delay from interconnects makes up a larger portion of total delay than does delay from transistors. And making all these layers of interconnects takes more process steps than making the transistors, so the interconnects also account for the largest proportion of production cost. Accordingly, the most effective way to simplify design, reduce power consumption, cut delay time, and reduce production costs will be to improve interconnect technology.
And oddly enough, one clear way to improve interconnect performance is to make the structures bigger. For 30 years, semiconductor circuits have gotten ever smaller, as smaller size reduced the transistor gate delay to speed up performance. But this scaling effect also brings some disadvantages, as the smaller patterns consume more power and increase delay on the interconnects. Semiconductors are now starting to reach the point where these effects interfere with performance.
Making the interconnects bigger reduces their resistance, so they can carry more current. Supplying the high amperage demanded by new high-power chips is an increasing problem. While low-power-consumption chips for wireless consumer electronics gear are also being developed, the main trend is clearly toward chips that consume more power. Some high-speed microprocessors now use 100W, and in 10 years some will use 200W, while their internal voltage will decrease from 2-2.5V down to around 0.5V. As power consumption increases and voltage decreases, amperage must sharply increase. In a few years, chips will use 100A. By 2014, the International Technology Roadmap for Semiconductors sees power consumption of 500A. Supplying this power with current technology will be a big problem. But using a giant 10mm connection for the power supply greatly reduces resistance, so the line can carry more amperage, and limits the decrease in voltage.
Larger interconnects with less resistance can also reduce the interconnect delay time. Longer interconnect delay times on ever smaller circuits will increasingly become a problem, especially for the clock signal. By the year 2005 or so, as interconnect length gets to 1mm, the delay on the clock circuit is likely to become greater than the cycle of the clock, so the clock signal will take longer than a cycle to get across the chip. Adding repeaters to the interconnect can reduce the delay, but the repeaters consume some 60% of its power. Using a 6mm interconnect reduces resistance enough so the clock signal can get across the chip in one cycle without repeaters.
For these giant interconnects to be practical, however, some way must be found to reduce their inductance, since large inductance can disrupt the signal into waves and cause variation in delay time. — Takayasu Sakurai, University of Tokyo
Case Study 2: Module with 15mm connections may match performance of systems chip
Combining DRAM, flash memory, and analog functions on one system chip once seemed like the ideal way to make high-speed, low-power devices, since multichip modules couldn't match one-chip performance. But it has turned out to be time consuming to develop these one-chip solutions, and expensive to make them. Now an alternative approach of connecting separate chips in stacks with 15mm-dia. microbumps looks like it can match a system chip in speed and power consumption, but with faster development time and lower cost.
The cost of making system chips will continue to increase, even as the design rules get smaller. One reason is that the voltage of some circuits can't be reduced much more, so the chip surface area taken up by those circuits can't be reduced either, making production more costly. These higher-voltage sections will also require several different types of gate-insulating films, necessitating multiple production processes. And of course, combining the different process technologies for DRAM, flash memory, and analog functions on the same chip is also difficult and costly.
Moreover, it takes longer to design a system chip than a single chip, and the whole chip is constrained to the parameters of its least advanced component. Designers can't use 0.15mm memory unless they can make 0.15mm logic, too. So system chips usually have to lag a generation behind the leading-edge design rule for some functions, which reduces their competitive edge.
Some systems chips even sacrifice the optimal performance of their individual parts. Since the combined units are made on silicon, high-frequency components usually made on gallium arsenide substrates won't work as well, or noise from the logic component can interfere with the analog circuits.
Joining separate chips in modules would solve all these problems, since the best chips made by any process could be easily and quickly combined, if the connections between the chips, and between the chips and the substrate, could be made cheaply, and could match one-chip performance. To this end, Matsushita is turning to miniature connections to join stacks of chips, using microbumps about 15mm in diameter. The incidental capacitance of these connections is only 10fF, so the module's speed and power consumption equal that of a single chip. With a 0.35mm design rule, the module is cheaper than a system chip if the chip area is greater than 80mm2. — Akira Matsuzawa, GM of the Advanced LSI Technology Development Center, Semiconductor Division, Matsushita Electric Industrial Co. Ltd.