Processing technology for integrated passive devices
11/01/2000
Brian Arbuckle, Elizabeth Logan, Intarsia Corp., Fremont, California
David Pedder, Intarsia Corp., Charlbury, Oxfordshire, UK
overview
Most of the devices in today's portable wireless products are passive components, and the integration of these components into a substrate or a separate device can provide significant performance, cost, and size advantages. There are many material and process options for fabricating these integrated passive components and devices, and these are reviewed here.
The latest portable wireless telephony, data, and Internet access products demand greater functionality, higher performance, and lower cost in smaller and lighter formats. This demand has been satisfied to date by major advances in silicon and GaAs integrated circuit (IC) device technology, and by the introduction of smaller packaging formats, smaller discrete passive components, and high-density interconnection printed circuit card technologies. The baseband sections of such products have benefited from system-on-a-chip (SOC) levels of monolithic silicon integration, while the RF sections have continued to require a range of active device technologies combined with high-performance passive components. This need to combine different technologies in RF functions has continued to be driven by exacting performance requirements, where a purely monolithic approach can involve too many performance compromises.
The relentless progress of active device integration and the trend toward greater functionality have also placed great pressure on the need to integrate passive components, especially in the RF sections of these wireless products. A typical cellular phone product may contain some 400 components, with fewer than 20 being active devices. The remaining 380 passive components can occupy around 80% of the phone circuit board area and contribute 70% of the product assembly costs. Therefore, technologies that can integrate passive components have a great potential to significantly reduce circuit board area and overall product size and weight, or to allow increased functionality at a given product size.
 Figure 1. Schematic cross-section of a thin-film integrated passive process. |
Increased manufacturing line throughput, reduced inventory, improved product reliability, and functional block and/or system level cost reductions are additional benefits that can follow from the use of integrated passive component technologies. These technologies can provide compact integrated passive device (IPD) network products or serve as a high functional density platform on which to combine the optimal set of active devices for the required RF function.
Integrated passive technologies
The three principal classes of integrated passive component technologies that are available today include thin-film technology, low-temperature co-fired ceramic (LTCC) technology, and technologies based on extensions of high-density interconnection (HDI) and other printed circuit board (PCB) technologies. The HDI and PCB technologies are most commonly employed in digital applications, where distributed capacitance and medium precision pull-up resistor functions can be realized at reasonable yield and cost. Of the technologies suited for RF integration, the thin-film integrated passive technologies generally provide the level of precision, range of component values, and functional density to allow a more integrated, smaller, and lighter implementation of a given RF function.
A schematic cross-section of a representative thin-film integrated passive process is presented in Fig. 1. This process provides a full range of resistor, capacitor, and inductor components, plus a low inductance ground plane structure and transmission line routing to interconnect the passive components. The thin-film structure is defined and supported on a suitable carrier substrate material. A key objective is to define a process that requires a minimal mask count (typically 6-10) and low process complexity while meeting the required component performance and accuracy criteria. The passive components themselves are generally constrained to occupy less than 1mm2 each in order to compete with discrete SMT components in both area and cost terms. A typical area of a processed thin-film integrated passive substrate showing examples of the three principal integrated passive component classes is illustrated in Fig. 2.
Resistors
The range of thin-film resistor values required for the vast majority of cell phone applications is between 10 and 100,000W. Simple linear resistor geometries in a single layer of 100W/square thin-film resistor material may be used for high performance RF resistors in the 10-1000W range. Serpentine resistors with minimum process geometry down to 5-10mm linewidth may be used where higher values are required. The thin-film resistor materials are selected primarily for their resistivity, processing compatibility, and temperature coefficient of resistance (TCR). Better than 0.5% tracking of adjacent resistors over temperature changes, 0.5% matching of adjacent resistors, and 0.5% stability under load performance are also usually required. Representative thin-film resistor material properties for integrated passive applications are presented in Table 1.
 Figure 3. Metal deposition plant for 350x400mm glass panels (Courtesy of Intevac). |
Tantalum nitride is probably the most widely used resistor material in thin-film passive technology because it offers a reasonable film thickness for a 100W/square film and a low TCR.
This material system also offers compatibility with dry etch pattern definition for high geometrical accuracy. These thin-film resistor structures are commonly defined early in the overall process sequence and are often located directly on the base substrate surface to maximize pattern definition accuracy and to aid thermal dissipation under load.
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Metallization uniformity and process patterning control are crucial to final component accuracy. Production metallization equipment is available for high uniformity resistor and conductor metal deposition for wafer processing and for large area panel (LAP) processing. A state-of-the-art LAP metal deposition plant for 350x400mm glass panel processing in an integrated passive production line is illustrated in Fig. 3.
Capacitors
A very wide range of capacitor values, from around 1pF to 100nF, is required to satisfy the full needs of both the RF and the baseband sections of a typical cell phone product. However, integrated passive technologies that can provide component values between 0.25pF and 500pF can meet all the requirements of typical RF IPDs, single-function RF modules, and complete RF module subsystems. Typical integrated passive capacitor processes employ two or more simple, nonferroelectric capacitor materials in classic metal-insulator-metal (MIM) capacitor structures to cover the range of values and performance required. The process interlayer polymer dielectric material itself may be employed for very low value capacitor values, with capacitance densities of around 5pF/mm2 for typical layer thicknesses. Intermediate capacitance values may be realized with plasma deposited silicon nitride films that give very good RF performance, with a low temperature coefficient of capacitance (TCC) for capacitance densities of 50-200pF/mm2. Higher value capacitors, principally for RF decoupling functions, may be realized with anodized aluminium oxide or tantalum oxide films at capacitance densities of 500pF/mm2 and above.
 Figure 4. An operator loading Applied Materials' PECVD SiN deposition system for 350x400mm LAP processing. |
Particular attention is given in the design of these integrated passive MIM capacitors to ensure low series electrode resistance and minimum parasitic capacitance to ground. These capacitor components have inherently very low parasitic inductance. Component structures and processes are tailored to ensure acceptable voltage breakdown strengths, generally guaranteeing a minimum value of 50V DC. A silicon nitride deposition system for integrated capacitor formation is shown in Fig. 4.
Inductors
Inductor components constitute less than 10% of the components in a typical cell phone product, with component values of 1-100nH, but they have a profound impact on overall RF performance. High quality factor inductors are essential to achieve suitably low phase noise performance in oscillator tank circuits and in the design of low loss passive filtering and matching circuitry. The variety of substrate and conductor materials for integrated passives allows very compact, high quality factor and high self-resonant frequency inductor components that are competitive with discrete SMT components in size, cost, and performance. They also outperform on-chip inductors in monolithic IC processes where the semiconducting silicon substrate losses limit performance.
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The inductor performance achieved is very much a function of the conductor material properties at the frequency of interest and of the design of the component. High-conductivity metals, such as copper or silver, provide the lowest losses, but performance at frequency is ultimately constrained by skin depth effects. An optimal metal thickness for lowest losses at a given frequency is 3-5 times the skin depth, and this rule-of-thumb may be used to gauge the thickness required to achieve low losses in an integrated passive inductor process.
 Figure 5. Solder bumped IC and MMIC devices, wire bonded discrete transistor, and wafer level, integrated passive substrate array prior to module assembly. |
Both single-layer and stacked spiral inductor components may be defined in a typical integrated passive technology, with stacked spiral inductor components giving a higher inductance/unit area by a factor approaching n2, where n is the number of stacked spiral layers. A typical two-level metallization process can therefore integrate inductor values from around 1nH to >100nH while consuming no more than ~1.5mm2/component. Through careful inductor design optimization and prudent choice of materials, inductor quality factors of 40-70 can also be achieved for inductor values of 1-20nH with self-resonant frequencies of 2.5-15GHz.
It should also be noted that SMT inductor components are considerably more costly than their companion resistor and capacitor components. This encourages minimal use of inductors in SMT-based designs. This penalty does not apply in an integrated passive environment, and a more inductor-rich design approach may be adopted, often with useful performance gains.
Multilevel metallization
The integrated passive resistors, capacitors, and inductors are interconnected by a multilevel metallization structure. This is typically a factor of 5-10 greater in thickness than usual for an IC process technology today. Thus, 5-15mm-thick interlayer polymer dielectric materials are commonly used, with aluminium or copper metallization layers 2-7mm thick. These layer thicknesses allow low loss inductors, and the low polymer dielectric constants permit coplanar or microstrip transmission line elements with impedances of 30-80Wm that have acceptable line losses at the usual metallization linewidths of 10mm and above.
 Figure 6. RF designer's selection pallet for integrated passive components and assembly components from a design library. |
A typical multilevel metallization process will provide two or three metal layers, with the lower layer (M1) commonly acting as the ground plane and as the lower plate of the MIM capacitor components. The higher metal layers (m2 and M3) provide transmission lines, routing traces, inductor spirals, and capacitor top plate connections.
The choice of polymer dielectric is crucial to the process architecture of the integrated passive process and has a significant bearing on the cost and performance of the overall process. Representative manufacturers' published data is presented in Table 4.
 Figure 7. Integrated passive devices (IPDs) in CSP format (0.5mm ball pitch). |
Other polymer dielectric materials properties, including thermal stability, moisture uptake, and elastic modulus, are also important in the interlayer materials selection.
Substrates
The substrate is the base layer upon which the integrated thin-film passive component process is defined, and it can have a significant bearing on the cost, yield, and performance of the final process. Common integrated passive process substrates include standard oxide-isolated silicon wafers, high-resistivity silicon wafers, glass wafers, and LAP glass materials developed originally for the thin-film display manufacturing industry. Both wafer and LAP formats take advantage of existing processing equipment capabilities and volume manufacturing infrastructure. The LAP formats have great promise for significant economy-of-scale benefits, with the display industry now employing panels up to 1m2 in area.
Process integration
The integration of the materials and components into a process flow follows a similar procedure to that of IC process development. Individual process modules are developed and then integrated to confirm whole process and materials compatibility, and to establish manufacturing process design rules. Care has to be taken in process architecture definition and materials selection to ensure good stability under load, suitable electromigration and ESD performance, moisture and corrosion resistance, and long-term microstructure stability.
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Component accuracies for resistor and capacitors in an integrated passive process are a function of layer thickness control limits and feature dimensional accuracy, and they vary with absolute component dimensions. Typical 3s limits of better than ±10% are achievable for components at and above 50mm minimum dimensions with tracking and matching normally better than 1%. Inductor values are determined essentially by the pitch and the number of turns of the inductor spirals. Since inductor pitch is a photomask-defined parameter, inductors can show variances of less than 1%.
Integrated passive module assembly
IPD network products may be assembled in a chip-scale package (CSP) format. Single function modules and complete RF transceiver subsystems may also be realized by the mounting and interconnection of active devices onto an integrated passives substrate. The die attach, wire bond, and solder attach pads in the integrated passive substrate require the addition of a solderable and wire bondable finish. A range of nickel-gold finishes is commonly used for this purpose.
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Active devices may be assembled and interconnected on the integrated passive substrate using an electrically conducting adhesive die attach process followed by wire bonding or using a flip-chip solder bonding process. Certain discrete active devices, such as varactor diodes — which require a back contact and are full, three-dimensional structures rather than planar device structures — will continue to demand wire bond assembly.
The general move to flip-chip assembly for RF ICs and other RF devices makes excellent use of the very low and reproducible bond inductance of flip-chip technology. The use of wafer level assembly for IPD ball attach, test, and tape-and-reel packaging, or for full module assembly and test, also adds to the cost-effectiveness of integrated passive technologies (Fig. 5).
 Figure 8. 2.45GHz VCO module showing wire bonded transistors and varactor diode on an integrated passive substrate (0.8mm ball pitch). |
Design methodology and examples
A robust design route is essential to ensure first time functional IPD and module designs and to minimize product time-to-market. While laser-based integrated passive component trimming is possible, the freedom to exchange components in the type of board level, iterative design route adopted for SMT products is not practical. Fortunately, it has been possible to develop highly accurate "parameterized" component models that fully describe the primary characteristics and the associated parasitic values of the components. Such models may be embedded as library elements in industry-standard RF design tools that allow design and circuit topology capture, circuit simulation, optimization, physical design, and layout and design iteration (Fig. 6). Design for process variability can also be taken into account. The use of this type of design methodology has resulted in a very high first-time-functional success rate.
Integrated passive technologies are being employed today in IPD devices and module designs at frequencies between 900MHz and 5.8GHz for a range of wireless communication applications (Figs. 7 and 8). The integrated passive processes themselves have been characterized and demonstrated at frequencies up to 50GHz.
Conclusion
Integrated passive component technologies can provide a high functional density medium for the cost-effective integration of RF passive networks, single function modules, and transceivers. The wide range of material and design options for resistive, capacitive, and inductive components allows a considerable degree of freedom in the modular, system-in-a-package integration of RF subsystems.
Brian Arbuckle received his BA in chemistry from the California State University, Sacramento, and his PhD in chemistry from the University of California, Davis. He joined Intarsia in 1998 and is currently the director of technology development. With more than nine years in the wireless technology industry, he is developing advanced components for the mobile wireless and computer markets and has authored more than 20 papers. Intarsia Corp., 48611 Warm Springs Blvd., Fremont, CA 94539; ph 510/403-6000, fax 510/403-6180, email [email protected].
Elizabeth Logan received her BS in metallurgy and materials science and her PhD in materials science, both from the University of Birmingham, UK. She joined Intarsia in 1997 and is currently the VP of research and development. With more than 15 years of experience in the materials and electronics industry, she is responsible for managing the company's key areas of research and development. She has authored more than 30 papers and holds two patent applications.
David Pedder received his master's degree in natural sciences and a doctorate in materials science from the University of Cambridge, UK. He joined Intarsia in 1999 and is currently the chief technology officer, with almost 30 years of experience in the wireless technology industry. He is a member of IMAPS, has authored 74 published papers, and holds 57 patent applications.