Eurofocus
10/01/2000
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ESEC addresses new flip-chip markets
New markets are emerging for flip-chip assemblies, and ESEC (Cham, Switzerland) is leveraging its strong position in the die bonder arena to address these in a new way. Instead of another new version of a flip-chip placement machine with optical alignment and the resulting slower throughput and higher cost, ESEC is modifying traditional die bonding equipment for placement of the low-pincount, low-accuracy flip-chip devices that are found increasingly in booming telecom and smart card applications.
Typically, high-end microprocessors with perhaps thousands of I/Os have driven the requirements of flip-chip assembly equipment, with capabilities such as <25 micron (3 sigma) placement accuracy. ESEC's Micron 2 for flip-chip, MCM, and direct chip attach is one such machine. The proliferation of low-pincount chips in new applications has created other market drivers and — in a rare step backwards for equipment makers — eased the requirements of the die placement machines.
Michael Orschel, a VP at ESEC and head of the die bonder business unit, said that ESEC has identified three such applications that benefit from flip-chip assembly in different ways: 1) RF devices that, like microprocessors, need the electrical performance; 2) smart cards that need the thinner assemblies possible with flip-chip; and 3) small logic devices that are adding functionality and need the better utilization of board space, with a larger flip-chip replacing a smaller device housed in an SO package.
All of these applications are low-pincount and do not require the placement accuracy needed by microprocessors and provided by costly optical alignment systems. Because of the less stringent alignment requirement, ESEC is designing a new model of its high-volume 2008 model die bonder to address this market, instead of using its slower flip-chip machine. The new model, 2008FC, will have a throughput of 3000-5000 UPH, compared to the typical flip-chip placement speed of about 1000 UPH. Production of the machine is expected to begin in the first quarter of 2001. — J.D.
Philips implements SOI for 2001 production
The Philips fab in Caen, France, is now implementing silicon-on-insulator (SOI) processes, and should be ready for production in mid 2001. The company will use the SOI process to produce chips for smart power devices, mobile phones, and automotive applications.
While the SOI wafers are said to cost almost 10 times as much as traditional wafers, Philips feels confident that the investment is worthwhile. Following a pilot study at the company's headquarters in Nijmegen, Netherlands, Philips expects SOI to increase chip speed by 30% and to reduce energy consumption by 50%.
"Smart power devices require chips that can handle both power and high-frequency components," says Gilles Ferru, process development group leader at the Philips Caen site. "The improved insulation using a SOI substrate allows us to maintain the same chip size, while increasing integration density."
Philips will also produce SOI chips for mobile phones, where BiCMOS processes are needed to integrate analog and digital signals onto the same device. The Caen fab was chosen for this implementation because of its expertise in BiCMOS and mixed signal processes. The SOI process will be implemented in collaboration with three French partners: Soitec (Grenoble) is supplying its Smart Cut technology; the Institut Superieur de la Matiere et du Rayonnement (ISMRA-Caen) is developing component characterisation, and the Institut Superieur d'Electronique du
Nord (ISEN-Lille) is in charge of process simulation.
"While SOI was slow to arrive at industrial utilization because of the substrate's complexity, we expect that the technology will boom in the next five years," says Daniel Diguet, communications director at the Caen fab. "Automotive applications will be another growth area for SOI technology, where we are planning devices that can sustain up to 60 volts."
EURO BRIEFS
Universal Display Corp., a leading developer of flat panel display technology, has entered into a development and license agreement with AIXTRON AG, of Aachen, Germany, to develop and fabricate organic light emitting device (OLED) production equipment. Using a transformational technology called Organic Vapor Phase Deposition, which was invented by scientists at Princeton University, the production process uses a carrier gas stream in a hot walled reactor at very low pressure for precise deposition of the thin layers of organic material used in OLEDs.
A 7.5-million-pound optoelectronics foundry, Compound Semiconductor Technologies Inc. (CST), was opened recently in the West of Scotland Science Park, Glasgow. The research center and III-V foundry will lead Scotland's (and the UK's) drive to become a leader in the global optoelectronics market. CST has brought together the research departments of the University of Glasgow and the University of Strathclyde to operate in one facility.