Asiafocus
10/01/2000
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First wafer-scale packages show up in commercial products
Only two years after the first conference papers outlined the new technology, the first wafer-scale chip packages are showing up in commercial products. Casio Computer Company Ltd. is using the compact packaging for microcontroller and flash memory chips in two new watches introduced in Japan this past summer (see figure).
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(Left) Casio analog-digital watch adds a dot matrix LCD to an analog face by using an Oki microcontroller in a REALCSP wafer-scale package by IEP Technologies: a) REALCSP wafer-scale package; b) the wafer before the packaged chips are cut apart; and c) the MTG series watch. (Right) Casio digital camera watch uses Fujitsu flash memory packaged in a Super CSP: d) the Super CSP wafer-scale package; e) the wafer before the packaged chips are cut apart; and f) the WQV series watch. (Photos courtesy of Casio)
Casio counts on packing its watches with multiple special functions to distinguish them from the competition. "So using wafer-scale CSP to shrink size and cut costs is essential," reports Takeshi Wakabayashi, VP of R&D at Integrated Electronics & Packaging Technologies Inc., Casio's joint venture with Oki Electric Industry Company Ltd. that is charged with developing the package technology.
Casio turned to wafer-scale packaging primarily to cram more chips onto a smaller circuit board. As the company tried to add more sophisticated features to new watch models, its designers could no longer fit more chips, and more pins/chip, onto a watch-sized circle using the usual chip-on-board packaging. Wafer-scale packaging of key chips and surface mounting allowed them to reduce circuit board area by about 30%, still using standard reflow mounting.
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Room to pack in more chips let the company make a watch that also works as a digital camera, using wafer-scale-packaged flash memory from Fujitsu Ltd., and one with both an analog face and a high-quality dot matrix liquid crystal display, using a wafer-scale-packaged microcontroller from Oki.
The other big appeal of wafer-scale packaging is its low cost. The technique uses no lead frames or package substrates and very little encapsulant, so material costs are low, and the cost of equipment declines when spread out over volume production. IEP isn't saying how much these initial packages cost, but Wakabayashi asserts that "in the future, it's bound to be cheaper than the old method."
Before it could use the wafer-scale packages, Casio had to find a suitable high-density substrate to put them on, and make sure of reliability. The company chose Matsushita Electronic Components' four-layer any layer via hole (ALIVH) board for the design freedom it offered, since the via holes could be put anywhere within the board. But because the board doesn't have the usual glass cross-fibers, it's relatively weak and bends easily, which would snap off the connecting leads of the wafer-scale packages attached to it. Therefore, Casio had to strengthen the board to make a more stable substrate.
Reliability of the package itself was not a problem (see the table, "Reliability test results," on p. 39). Because the wafer-scale package uses so little resin that can absorb moisture, there were none of the usual problems with trapped moisture expanding in the heat of processing and bursting the package.
The package meets Japan's Joint Electron Device Council's Level 1 standards. However, the reliability of the package connection to the board was more problematic, since the thermal expansion of the silicon chip does not match that of the plastic board. So Casio adjusted the composition of the resin, the height of the solder balls, and the height of the copper posts to achieve acceptable reliability for 0.5mm pitch connections.
"It looks like the current process will work down to 0.3mm pitch," notes Wakabayashi. — Hiroshi Asakura
*This story was translated for SST from the June 2000 issue of Nikkei Microdevices, our partner in Japan.