A re-examination of silicon wafer specifications
10/01/2000
Howard R. Huff
 |
The smaller dimensions associated with continued transistor scaling offer the opportunity for a detailed re-examination of the role and usefulness of silicon wafer specifications. Data is being developed that suggests a reduction of various contaminants and defects in silicon wafers may not necessarily be required to ensure continued improvements in IC performance, although detailed yield and reliability studies are still required to fully quantify these observations.
Today, device scaling has resulted in transistor gate delay approaching <1psec for gate length critical dimensions (CDs) <40nm. MOS transistor switching has already been demonstrated to ~18nm, with possible scaling to 10nm in an innovative transistor configuration. Concurrently, the decrease in operating voltage is especially important, reducing the propensity for gate dielectric leakage, junction breakdown, and latch-up.
Some implications
The conventional trend in silicon wafer characteristics has often consisted of increasingly tighter specifications so as to match the current sensitivity limits of metrology tools. A shift occurred during the 1990s, however, with an increased emphasis towards the scientific understanding of the physico-chemical properties and processes in silicon, the selective application of design of experiment methodologies, and model-based silicon wafer criteria for the International Technology Roadmap for Semiconductors (ITRS). Accordingly, it became necessary to balance the "best wafer possible" against the cost of ownership (CoO) opportunity of not driving silicon requirements to the detection limit, but to some less stringent value consistent with achieving high IC yield.
 |
There has been significant literature data supporting the latter [1]. Consider, for example, thc implications of ultra-thin gate dielectrics on the specification of metals and crystal originated pits (COPs); it may be less stringent than for the case of thicker gate dielectrics. A quantitative model of gate oxide breakdown suggests that a singular behavior is reached in the oxide thickness regime approaching 2nm or so when the effective defect size becomes comparable with the oxide thickness. Indeed, recent experiments on 5-17nm oxides indicate the reduced influence of critical metals such as Ni at 1011/cm2 and higher on the charge-to-breakdown, QBD, with reduced oxide thickness. Investigations are required, however, to assess the implications of these observations for time-dependent dielectric breakdown (TDDB). Furthermore, wet chemical cleaning efficiencies greater than 95% for critical metals such as Fe have been demonstrated. Accordingly, an incoming critical metal specification of ~1011/cm2 may operationally result in <1010/cm2 on the silicon surface after cleaning. Although it may be disconcerting to specify the incoming wafer critical metals in the range of ~1011/cm2, the viability of driving initial critical metals <1010/cm2 may be inappropriate from a CoO perspective.
Other considerations
Similar considerations for particle density may be applicable when considering the wet chemical cleaning efficiency prior to thermal processing. Additionally, it may be that taking the particle size equal to 90nm (50% of the CD at the 180 technology generation) through the 130nm node may not be as detrimental as previously envisioned due to an improved particle distribution. It is very useful from a metrology and CoO viewpoint, moreover, to specify the particle density required at a given CD in terms of the equivalent, smaller number of particles at a larger CD, as described by the (assumed) usual inverse square power law.
As the oxide thickness decreases to ~5nm, the influence of COPs and related flow pattern defects on gate oxide integrity (GOI) has been found to become negligible for Czochralski (CZ) polished wafers. Accordingly, the efficacy of using "perfect" CZ silicon, while a remarkable scientific achievement, must be reassessed for future generations of ICs fabricated in CZ polished wafers from a CoO perspective. Here, also, TDDB studies are required.
Of course, there are additional issues besides GOI that must be considered, since COPs can also impact IC isolation and leakage failures. Epi layers >100nm or so, furthermore, essentially cover up COPs in lightly doped substrates, essentially negating their influence, while COP formation in heavily doped p-type substrate wafers is suppressed. (The reduction of the epitaxial-to-polished wafer cost ratio for 300mm wafers favors the continued use of epitaxial wafers for logic applications and may signify its use for other applications, such as memory circuits that have typically been manufactured on lower-cost CZ polished wafers. In that regard, the utilization of "perfect" CZ polished wafers may also require CoO consideration as to its viability as substrates for epitaxial structures.)
A UV-Cl2 clean can reduce surface microroughness (Rrms) to ~0.1 ±0.01nm, with significant improvements in both QBD and (effective) tunneling barrier height. Oxide thicknesses in the range of 1.3-4.0nm exhibited similar Rrms using the UV-Cl2 clean. The influence of cumulative thermal processing during IC fabrication on Rrms, however, also requires cognizance since both roughening and smoothing can occur as independent mechanisms under some oxidation conditions. Accordingly, the viability of driving the initial Rrms <0.1nm, which can readily be achieved today, may not be justified from a CoO viewpoint.
The utilization of multiple-well structures fabricated by ion implantation in effect decouples the transistor from the original silicon material characteristics, thereby reducing its sensitivity to the initial resistivity, tolerance, and uniformity for both CZ polished and epitaxial substrate wafers. Whereas the nominal substrate doping for epitaxial wafers is typically in the range ~5-10mW-cm to ensure latch-up control, shallow trench isolation is rendering classical concerns for latch-up, such as n+- p+ spacing, moot. Accordingly, resistivity ranges >20% may not be inappropriate, also favorably impacting CoO.
Internal gettering (IG) in CZ polished silicon wafers may still be required to remove deleterious metallic contaminants inadvertently introduced during IC processing. A ±2ppma variation in bulk oxygen concentration in the range ~18-31ppma (old ASTM standard) may be sufficient to ensure stringent bulk defect control with acceptable homogeneous IG capability. Adequate wafer strength and resistance to warpage, along with denuded-zone width control, is also required. Methodologies have recently been developed, moreover, wherein IG is independent of the bulk oxygen concentration, the details of the crystal growth process, and, to a large extent, the details of the IC fab thermal processes, but essentially dependent on the local vacancy concentration in the thermally treated wafer prepared by the silicon supplier. The utilization of a heavily doped p-type substrate for epitaxial applications, however, also offers an effective CoO gettering system via the Fermi effect.
It thus appears that the reduction of various contaminants and defects as well as the continued reduction of certain other wafer specifications may not necessarily be required to ensure continued improvements in IC performance, although detailed yield and reliability studies are still required to fully quantify these observations. It would, of course, be advantageous to put this approach on a firmer basis. Unfortunately, in spite of about 35 years of IC fabrication, current models do not sufficiently establish the real requirements for parameter uniformity or the effects of parameter variability on IC properties.
Detailed understanding of silicon issues in relation to IC design and process technologies remains a significant scientific opportunity with far-reaching CoO implications. Development of such models, in conjunction with statistical specifications, is essential to enhance the utility of future Roadmaps.
Acknowledgment
The author appreciates extensive discussions with the 1999 Starting Materials ITRS sub TWG team.
Reference
- "Silicon Wafers for the Mesoscopic Era," ECS Symposium on Electronic and Photonic Materials for the 21st Century (May 14-18, 2000) (PV 00-01, abstr. #405). A modified version was presented and will be published in the proceedings of the 2000 International Conference on Characterization and Metrology for ULSI Technology, June 26-29, 2000, AIP Press, 2001.
Howard R. Huff is senior fellow and materials science program manager at International Sematech, 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-3334, fax 512/356-7640, e-mail: [email protected].