Furnace-based rapid thermal processing
10/01/2000
Jeffrey Hebb, Ali Shajii, Matt Flynn, Axcelis Technologies Inc., Peabody, Massachusetts
Additional authors are listed in the Acknowledgments.
overview
Semiconductor manufacturers using RTP have traditionally been limited to the use of variable intensity, lamp-based systems of increasing complexity and cost. Here we describe an alternative approach — a simple, effective, furnace-based RTP. The tool described is the Axcelis Summit RTP system, with the main focus on its wafer temperature uniformity, measurement, and control. Thermal performance is demonstrated with standard implant anneal process results. In addition, experimental results are presented to illustrate advanced process capability such as spike anneal, CoSi anneal, and ultra-thin gate oxide formation.
 Figure 1. Schematic of the Axcelis Summit furnace-based RTP system. |
A schematic of the Summit rapid thermal processing (RTP) system is shown in Fig. 1. The heating source is an axisymmetric silicon carbide bell jar that is heated by a three-zone furnace. The base of the bell jar is water cooled, so that a vertical thermal gradient is established. Three spike thermocouples (TCs) are used to measure the bell jar temperature at all times. Before a process begins, the required thermal gradient is established by adjusting the zone powers until the desired spike TC setpoints are reached. The zone powers continue to be actively controlled during wafer processing to maintain this stable thermal environment. The Summit is an atmospheric system, with ambient control achieved by flowing process gas through a quartz injector tube, as well as through the elevator tube.
To begin processing, the wafer is placed on a quartz wafer holder that sits on a quartz elevator tube. The wafer temperature is then changed by moving the wafer in the vertical direction inside the reactor. The temperature trajectory of the wafer is determined by its position trajectory and radiative properties. Typically, the spike TCs are set so that the top of the bell jar is approximately 200°C higher than the desired processing temperature. Wafer temperatures up to 1200°C and ramp rates of up to 150°C/sec can be achieved in the system. During processing, the temperature at the center of the wafer is measured using an emissivity compensated pyrometry system. The measured wafer temperature is then used in conjunction with real-time model based control of the elevator position to produce the desired time-temperature profile.
Within-wafer temperature uniformity
The heating source in the Summit is fundamentally different from that of lamp-based RTP systems, in that it is spatially continuous, axisymmetric, and, most important, it is in quasi-thermal equilibrium with the wafer. The system is designed so that as the wafer approaches its processing temperature, it also reaches near thermal-equilibrium with the heating source (the bell jar). For a given bell jar thermal profile, there is a range in the vertical direction (typically at the top half of the bell jar) in which a highly uniform temperature across the wafer is maintained. This situation prevails both in steady state and transient conditions (ramp up or down). To a first approximation, moving the wafer into this optimum processing zone is equivalent to placing it in an isothermal black cavity. It is well known that in such a cavity, a body will achieve a uniform temperature [1]. (This fundamental concept is the basis for the good thermal performance of batch diffusion furnaces.)
 |
Figure 2. Temperature dependence of the spectral emissivity of a film stack consisting of 1500Å poly-Si/2000Å SiO2.
Additionally, in the Summit system, the wafer temperature uniformity can be fine-tuned by adjusting the thermal gradient of the three-zone furnace.
In fact, we have developed detailed computational models to guide the optimum selection of the spike TC setpoints, resulting in highly uniform temperature distribution on the wafer [2]. In what follows, detailed experimental results are presented to show the performance of this system as it relates to temperature uniformity.
Wafer temperature control
The temperature trajectory of the wafer is determined by the elevator position trajectory and the radiative properties of the wafer. Therefore, control of a specified time-temperature profile is achieved by moving through the appropriate elevator position trajectory. The approach provides some advantages for temperature control:
- Since the system inherently delivers within-wafer (WIW) uniformity, only the temperature at the center of the wafer needs to be measured and controlled. This reduces the complexity of the control problem to a single-input single-output (SISO) — as opposed to a multivariable — control problem.
- The quasi-thermal equilibrium nature of the system mitigates the effect of variations in wafer radiative properties and the associated thermal response of the wafer. Thus, different wafers will not have drastically different position trajectories in order to achieve the same temperature profile (trajectory).
- Since the heating environment is highly stable and repeatable, the only variable that needs to be controlled is the elevator motion. Sophisticated and robust motion control systems have been developed in a number of different industries that allow micron-level position tracking and control.
- The same principles of uniformity and control apply regardless of processing temperature.
This fundamental heating concept makes it a simple and robust way to achieve RTP. However, one must still have a state-of-the-art temperature measurement and control system to meet the demanding thermal and process performance requirements for future device generations.
Emissivity-compensated temperature measurement
Accurate noncontact wafer temperature measurement has turned out to be one of the most challenging problems for RTP over the last decade. Critical applications such as source/drain anneal require wafer-to-wafer repeatability pushing the envelope of "traditional" pyrometry. To make accurate wafer temperature measurements using pyrometry, the emissivity of the wafer backside at the pyrometer wavelength must be known. Typically, production silicon wafers have backside films that can drastically alter the spectral emissivity through interference effects, potentially causing large temperature measurement errors for standard pyrometry. Furthermore, the emissivity is generally dependent on wafer temperature and backside surface roughness [3-6]. All of these factors make real-time in situ emissivity compensation a requirement to achieve acceptable temperature measurement accuracy. Typical variations of emissivity are illustrated in Fig. 2, which shows the predicted spectral emissivity of a poly/oxide wafer at room temperature and at 1050°C [7]. The emissivity at a typical pyrometer wavelength such as 950nm changes from 0.35 to 0.20 as the wafer is heated from room temperature to 1050°C. This is mostly due to the temperature-dependent refractive index of the polysilicon layer. In this case, if the variations of emissivity with temperature are neglected, as much as 80°C error is encountered in the measured value of temperature.
The objective of the emissivity compensation system is to measure the emissivity, e, of the wafer backside during the processing of a wafer [8]. This is achieved by determining the hemispherical directional reflectivity of the wafer backside, and applying the following equation:
 |
[1]
where e is defined as the normal emissivity averaged over the spectral range Dl, and R is the hemispherical directional reflectivity in the normal direction, also averaged over the spectral band of the pyrometer. The hemispherical directional reflectivity in the normal direction is defined as the reflectivity one would measure by illuminating the target uniformly and hemispherically, and collecting the reflected light in the normal direction [1]. Our objective is to measure R during processing at the center of the wafer in a system (inside the bell jar) where it is very difficult to achieve the conditions of uniform hemispherical illumination. Thus, a combination of ex situ and in situ reflectance measurements are used to achieve the high-precision results presented here.
Before the wafer is brought into the processing chamber, it is automatically placed on an integrating sphere that meets the conditions of uniform hemispherical illumination. The room temperature hemispherical directional reflectivity of the wafer, denoted by Ro, is determined from a calibration curve created using NIST traceable reflectivity standards.
 |
Figure 3. Average sheet resistance for wafers with varying backside emissivities (1040°C/10-sec anneal).
Once Ro is obtained, the wafer enters the processing chamber, where a relative reflectivity measurement is performed to obtain the change in reflectivity during the process. Chopped light is introduced into the chamber and directed to the wafer backside. The total radiative flux from the wafer center (in the normal direction) is collected by the pyrometer head, which is fixed at the bottom of the quartz elevator tube. The total radiative flux is composed of the thermal radiation emitted from the wafer and the reflected portion of the chopped light. The magnitudes of the emitted radiation and the reflected chopped light are determined by an advanced signal processing system. The change in the magnitude of the reflected chopped light throughout the process is used to calculate the change in reflectivity of the wafer backside. The real-time emissivity is determined from Eqn. 1, and then used to convert the measurement of the emitted radiation intensity into wafer temperature.
The optical system is calibrated for absolute temperature using a blackbody furnace on the benchtop. This is a valid calibration, as there are minimal multiple reflections of emitted light in the system. This allows us to get within a few degrees of absolute temperature, resulting in tool matching of ±2°C. Note that no test wafers, thermocouple wafers, or monitor wafers are required to calibrate the in situ emissivity compensation system.
 |
The effectiveness of the emissivity compensation system is evaluated by performing a series of implant anneal experiments. The wafers used had various backside films that yielded an emissivity range of 0.20 - 0.76 at the pyrometer wavelength. The backside layers and emissivity of each wafer type are shown in Table 1. Four wafers of each type were annealed at 1040°C for 10 sec, using an average ramp rate of 65°C/sec. All wafers have the same frontside implant (As, 1x1016cm-2, 25keV through a 100Å screen oxide), which is used to infer wafer temperature. The sheet resistance of each wafer was measured using a four-point probe after stripping the screen oxide. Figure 3 shows the average sheet resistance for each wafer. The sensitivity for this implant is approximately 1W/sq/°C, so the results show a total range of 4°C for all wafers, and a wafer-to-wafer (WTW) repeatability of 3.2°C (3s). This corresponds to an accuracy of ±0.005 for the emissivity measurement. Similar results have been achieved using thermal oxidation to infer wafer temperature.
Wafer temperature control
Given the inherent advantages of SISO control on the Summit, the question becomes how to drive the elevator to achieve the desired temperature trajectory. The ideal control system is one that accurately tracks desired ramp rates with minimal overshoot or undershoot for all wafer types. The main obstacle to achieving this is the unpredictable differences in the radiative properties of the wafer frontside and backside due to blanket films and device patterns.
In the Summit system, standard proportional integral derivative (PID) control schemes are not effective for a number of reasons. These include: a) nonlinearity of the system (radiation heat transfer); b) large variations of the temperature during processing within only a few seconds; c) variations of the wafer surface properties that can affect its "effective" thermal mass; and d) the fact that overshoots are not tolerated, eliminating a large gain as an option. The general idea behind the model based control is that if one has a physical model that can predict the relationship between the input variable (T) and the output variable (z), this provides a "look-ahead" capability that allows tighter control. In a model based temperature control (MBTC) scheme, one is only correcting for discrepancies between the predicted and measured temperatures, which in general is small. The main requirements on the model are good accuracy and minimal computational intensity, which allow real-time solutions.
The mathematical details of the wafer temperature model have been described elsewhere [2]. In summary, to develop a model for the wafer temperature, the general three-dimensional heat equation for the wafer is reduced to an ordinary differential equation that represents the average wafer temperature:
 |
[2]
 |
where T is the average wafer temperature, r is the wafer density, C(T) is the wafer heat capacity, ef and eb are total emissivities, af and ab are total absorptivities, and qf and qb are total incident heat fluxes averaged over the wafer radius. Subscripts f and b denote wafer front and backside, respectively. As an approximation to the total radiative properties of a product wafer, we assume that the wafer is bare and lightly doped silicon. The temperature dependent radiative properties are calculated once using thin film optics theory and are then built into the model. Next, for a given furnace spike setpoint, the temperature distribution of the bell jar is determined and is then used as a known heat source to the wafer. For a given wafer position, the differential view factors from the bell jar to the wafer are calculated and integrated over the total areas to obtain qf and qb. Thus, for a given input z(t), the output is T(t).
The goal of model-based temperature control is to use Eqn. 2 in real time to guide the elevator trajectory during processing. In order to achieve this goal, we first invert Eqn. 2 and solve for the wafer height as a function of wafer temperature and rate of temperature change:
z = z (T, dT/dt) [3]
 |
Figure 4. Results of model-based control for a) a bare silicon wafer, and b) wafers with different backside films.
If the radiative properties of the wafer were known exactly, and the bell jar temperature profile was highly accurate, Eqn. 3 would be used to drive the elevator for a specified temperature trajectory. However, since Eqn. 2 is only an approximation of the physical system, and the radiative properties generally vary from wafer to wafer, we need to utilize Eqn. 3 with a feedback servo to obtain acceptable performance. Specifically, two techniques are used to obtain trajectory tracking: a) feedback linearization, and b) a novel "adaptive" approach that takes advantage of the discrete nature of the algorithm implementation. The algorithm is described in detail elsewhere [9].
 |
Figure 4a shows results for a silicon wafer, for a 70°C/sec ramp to 1050°C, with a 1.4-sec "roll over" time, then a ramp-down rate of -50°C/sec. The plot shows the wafer temperature, elevator position, and instantaneous ramp rate. From the ramp rate trace, one can see that the MBTC is effective for tracking ramp rates with minimal overshoot/undershoot for bare silicon. Figure 4b shows the same recipe run on three other wafer types with a variety of backside films. Two of the wafers are low-emissivity poly/oxide wafers with varying poly-Si thicknesses (types 1, 2, and 5 from Table 1). The time-temperature traces for all of the wafers are very similar, with excellent ramp rate control, and overshoots less than 2°C for all wafers. The results show that the model-based temperature control scheme is effective in making the control system immune to variation in wafer radiative properties. Similar results were obtained for a set of wafers with varying frontside radiative properties.
 |
Total temperature variation
To evaluate the total repeatability and uniformity for the system, a five-day repeatability study was conducted using implant anneal. The wafers are 200mm bare Si wafers that have been implanted with boron (2keV, 2 x 1015cm-2). They were annealed at 1000°C for 10 sec with a 65°C/sec ramp rate. The sheet resistance was measured at 49 points with a 6mm edge exclusion. The sensitivity of this implant for this anneal is 2.5W/sq/°C. A total of 70 bare silicon wafers were annealed, distributed throughout multiple cassettes each day such that across-cassette, cassette-to-cassette, and day-to-day repeatability could be evaluated. Table 2 shows the average WIW uniformity for the 70 wafers and the total WTW repeatability for all 70 wafers. Also shown in the table is the WTW repeatability for wafers with varying backside films. Adding these three components of temperature variation in quadrature gives a total temperature variation of 3.7°C (3s).
 Figure 5. a) Thermal profiles for spike anneals across a cassette, and b) across-cassette repeatability and uniformity for 1050°C spike anneal. |
Spike anneal
For future device generations, spike anneals will be required for source/drain activation in order to achieve sufficient electrical activation while avoiding excessive diffusion. Achieving acceptable WIW uniformity and WTW repeatability while maintaining a small thermal budget is a current challenge for RTP systems. The advantages of the furnace-based RTP demonstrated above for standard anneals also extend to spike anneals. We evaluated the WIW uniformity and WTW repeatability for spike anneals in a five-day repeatability study similar to the one described above for 10-sec anneals. The implant was boron (500eV, 2 x 1015cm-2), and the recipe was a spike anneal with a maximum target of 1050°C. The sensitivity for this anneal was 4.5W/sq/°C. Thermal profiles from seven wafers distributed throughout one cassette are shown in Fig. 5a. The thermal profiles demonstrate the repeatability delivered by the Summit control system, where the range of maximum temperatures is better than ±1°C. The wafer spends a total time of 2.5 sec above 1000°C. Figure 5b shows the average sheet resistance and WIW uniformity for these seven wafers, and Fig. 6 shows a typical sheet resistance uniformity map. For the 70 wafers run over the course of the five-day study, the average uniformity was 2.7°C (3s) and the overall repeatability was 1.7°C (3s). The uniformity validates the claim that the quasi-thermal equilibrium state of the tool delivers uniform temperature during transient wafer heating and cooling.
 |
Figure 6. Typical sheet resistance map for spike anneal (boron, 2keV, 2x1015cm-2, 1050°C spike). Uniformity is 0.7% (1s) and 2.4°C (3s).
Low-temperature processing
Low-temperature processing for applications such as cobalt silicide formation, copper annealing, and low-k annealing are also a challenge for RTP systems. Again, the furnace based approach to RTP offers advantages for low temperature processing. The across wafer temperature uniformity is excellent at low temperatures, and the heat flux delivery system, i.e., the bell jar and the elevator, remains stable and easily controllable. We have evaluated the low temperature uniformity and repeatability through a 400°C/30 sec CoSi process. The results demonstrated an average uniformity of 1.7°C (3s) and repeatability of 1.4°C (3s).
Conclusion
The advantages of furnace-based RTP have been described and demonstrated through process results on the Summit RTP system. Using an advanced temperature measurement and control system, excellent thermal performance has been demonstrated for standard processes as well as advanced processes such as spike annealing, steam oxidation, and low temperature processing. n
Acknowledgments
Additional authors of this article are Peter Frisella, Sharon Szelag, Jian Zhang, and Bob Couilliard of Axcelis Technologies Inc.
References
- R. Siegel, J.R. Howell, Thermal Radiation Heat Transfer, Hemisphere Publishing Corp., Washington, DC, 1992.
- A. Shajii, J.Hebb, B. Matthews, "Temperature Control and Uniformity in a Furnace-based RTP System," 7th International Conference on Advanced Thermal Processing, 1999.
- P.J. Timans, in Advances in Rapid Thermal and Integrated Processing, p. 35, ed. Fred Roozeboom, Kluwer Academic Publishers, The Netherlands, 1996.
- J.P. Hebb, K.F. Jensen, "The Effect of Surface Roughness on the Radiative Properties of Patterned Silicon Wafers," IEEE Trans. on Semi. Man., Vol. 11, p. 607, 1998.
- P. Vandenabeele, K. Maex, "Emissivity of Silicon Wafers During Rapid Thermal Processing," Proc. SPIE, Vol. 1393, p. 316, 1990.
- C. Schietinger, in Advances in Rapid Thermal and Integrated Processing, p. 103, ed. Fred Roozeboom, Kluwer Academic Publishers, The Netherlands, 1996.
- J.P. Hebb, Pattern Effects in Rapid Thermal Processing, PhD Thesis, Massachusetts Institute of Technology, 1997.
- J.P. Hebb, A. Shajii, "Wafer Temperature Measurement in a Furnace-based RTP System," 7th International Conference on Advanced Thermal Processing, 1999.
- A. Shajii, B. Matthews, J. Hebb, J. Danis, "Robust Temperature Control in a Furnace-based Rapid Thermal Processing System," to be submitted to IEEE Trans. On Automatic Control, (awaiting patent filing).
Jeffrey Hebb received his BEng in mechanical engineering from the Technical University of Nova Scotia, and his MSc and PhD in mechanical engineering from the Massachusetts Institute of Technology. He joined Axcelis Technologies in 1997; he presently manages the applications group in Axcelis' Thermal Processing Division, where he focuses on advanced RTP. Axcelis Technologies, 2 Centennial Drive, Peabody, MA 01960; ph 978/524-6434, fax 978/524-6444, e-mail [email protected].
Ali Shajii received his BS from the University of Wisconsin-Madison in engineering physics in 1990, and his PhD in nuclear engineering from the Massachusetts Institute of Technology. After working at MIT and Astex Inc., he joined Axcelis, where he is the program manager for the Summit 300XT. His interests are in systems and control engineering and heat and mass transfer.
Matthew Flynn is the product line manager for the Axcelis thermal processing systems group. Prior to joining Axcelis, he held sales and marketing positions at Cherry Semiconductor, Teledyne, and Hybrid Components.