Improve yields, enhance CDs with integrated DUV resist track
10/01/2000
COVER ARTICLE
Murthy Krishna, Emir Gurer, Tom Zhong, Eddie Lee, John Salois,*
Silicon Valley Group, Track Systems, San Jose, California
*Additional author is listed in the Acknowledgments.
overview
Detailed attention to the design of resist processing nozzle rinsing action and improved airflow around the developer catch-cup chamber, combined with physical process-parameter optimization, has achieved a significant reduction in defects during resist processing and wider process latitude. The overall effects include yield and throughput improvements using deep-UV resists, which translate into enhanced cost of ownership, and the potential of minimizing chemical and deionized water consumption to meet stringent environmental regulations. Further, we believe that the results presented here are applicable to smaller geometries and to 300mm wafers.
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Each generation of new semiconductor device technology becomes cost-effective only because of improving manufacturing productivity and demonstrated profitable cost of ownership (COO). Within lithography operations, minimization of defects in the resist development process has become of paramount importance. Reduction of deionized (DI) water and chemical consumption is also critical if resist developer modules are to meet stringent environmental regulations.
In addition, the impact of adhesion reduction due to smaller contact area between feature and substrate becomes significant. Considerable yield improvement can be realized by preventing pattern collapse of smaller features during develop and rinse processing [1]. Along with this, lower viscosities of resist materials and decreasing thickness result in increased defect densities at the film-substrate interface.
Accordingly, understanding the nature of the wafer surface, developer, and resist surface interactions, film interface interactions, and their impact on defect reduction, is becoming increasingly significant.
Numerous studies have identified the resist-develop step as the source of the majority of post-develop particles [2-5]. Therefore, improving the develop-and-rinse process can reduce particle contamination. Traditionally, many of the schemes undertaken to reduce particles penalized process throughput because they use extended rinse times in the develop process. It was our objective to reduce particle generation for an advanced deep-UV (DUV) lithography, sub-0.25µm process and simultaneously locate the shortest rinse time, thereby increasing throughput and the develop process window.
We found that defects can be reduced by improving rinsing action through enhanced rinse nozzle technology, improving airflow around the developer catch cup chamber, and improving mechanical rinsing effectiveness via physical-process parameter optimization. A good rinse nozzle design must have multiple orifices that provide uniform coverage and reduce impact forces near each orifice through optimized geometry. A good developer catch-cup chamber must be based on computational fluid dynamics simulation and modeling and rigorous experimental flow visualization.
 Figure 1. Defect counts vs. rinse time and spin speed for a) standard rinse nozzle and b) enhanced rinse nozzle. |
At resist processing, a key to achieving defect reduction and maximizing yield is to focus on the developer module of the track system where the majority of defects are created. For optimum defect reduction, the rinse nozzle should provide good liquid distribution, uniform coverage of the wafer, excellent rinsing action and low impact on the wafer. These allow significant CD uniformity improvement without compromising defect reduction and yield enhancement. The developer catch-cup chamber should provide a uniform air-velocity field to reduce turbulence, back flow, and recirculation. An optimized process to leverage the maximum benefits from the rinse nozzle and catch cup chamber is also required. An all low-impact rinse-and-develop chemical-delivery system was designed to eliminate pattern collapse of features from 180nm to 100nm.
In the end, ours was a chamber aerodynamically balanced for uniform air-velocity field and minimum turbulence. This eliminated back flow, recirculation, and redeposition of particles onto the surface of the wafer. Our work optimized the physical process parameters, including rinse time, spin speed during rinse and dry steps, accelerations during the dry cycle, the rinse nozzle position, exhaust flow rate, and the number of rinse steps.
CD control
The main components of critical dimension (CD) control in DUV lithography are scanner, track, etch, substrate, and metrology [6]. The main wafer-track contributors to CD variation are resist thickness uniformity and mean thickness control, post exposure bake (PEB) temperature uniformity, post apply and post exposure timing delays, and the develop process [7].
The material properties and performance of the photoresist, coupled with track and scanners, are also critical contributors to CD control.
 Figure 2. Radial distributions of develop rates in the sub-develop test for standard and enhanced develop nozzle for type A resist. |
The contribution of the develop process to CD budget is changing and its role is increasing. For advanced 248nm DUV lithography to attain geometries down to 100nm, high-contrast and high-sensitivity resists are needed. For these resists, attaining excellent develop-rate uniformity places special demands on chemical delivery systems.
The enhanced develop nozzle resulting from our work has multiple orifices that provide a more uniform coverage and reduce the impact forces near each orifice through its optimized geometry. We found that the critical develop process parameters that impact develop-rate uniformity and CD uniformity are: the number of dispense steps, the time of dispense, the type of dispense, dispense spin speed, ramp down to puddle, dispense height, and the position of dispense.
The sensitivity of develop rate and CD uniformity to these parameters and CD control varies for different families of resists. Thus, it is important to understand the fundamental mechanistic behavior of these resists with respect to the develop process.
Integrated hardware approach
The uniqueness of our project was an integrated and synergistic approach to yield and CD control for advanced DUV lithography. To overcome the difficulty in completely decoupling yield management and CD control from each other, we designed an integrated rinse and develop nozzle system to achieve low-impact, fast, and improved liquid delivery over the entire wafer.
The advantages of an integrated hardware approach include: liquid delivery on demand, with no time delays and fast transitions between steps, flexibility in important process steps such as overlapping rinse and developer dispenses, and only low-impact flows are present throughout the develop process.
Process variables to optimize yield and CD are not always aligned in the same direction. The parameter space, which gives optimum yield, might compromise CD control, and vice versa. Therefore an integrated approach is necessary.
Experimental approach
For this development work, we used an SVG Lithography Systems Micrascan II scanner and an advanced track system. Using monitor wafers, we first established baseline SPC thickness, CDs, and defect density. We used low activation energy acetal-based DUV resist (resist type A) for defect reduction. For the CD control project, after the feasibility and the performance improvements with the enhanced nozzle were validated with resist type A, we conducted extensive develop process CD optimization using a type B negative tone DUV resist. Finally, we obtained rigorous CD results on silicon-oxynitride-coated wafers using a type C resist—an ESCAP-based positive tone DUV resist with high activation energy. (ESCAP resist is an environmentally stable DUV photoresist for 248nm exposure.)
To identify an optimum set of parameters, we performed a six-factor design-of-experiments test. Factors examined included physical process parameters, such as rinse spin speed, rinse time, acceleration during dry cycle, nozzle type, rinse time algorithm, and chemical injection. The process responses optimized were total develop process time and defect density. We used coated, unexposed, unpatterned wafers that had been processed in a cluster tool (i.e., a track system linked to an exposure tool) through the full process flow. This allowed efficient collection of particle data using an unpatterned wafer inspection tool and simulated defect generation on a contact layer (<5% exposure area on the wafer). The inspection tool was a Tencor 6420 Surfscan laser scanning system that counted defects >0.2µm, large clusters, and area defects. Laser scanning is highly sensitive to surface defects, allowing detection of common photodevelop defects such as particles from precipitation, developer and film residues, and surface roughness.
CD control
We used develop rate and CD uniformities as comparative performance metrics for both enhanced and standard nozzles. The conventional E0 (i.e., the minimum dose required to completely clear the resist film) uniformity test, as a measure of the quality of a develop process, has serious limitations because it is visual, subjective, and has limited resolution. On the other hand, develop rate uniformity obtained from the sub-develop or sub-E0 tests is less subjective and is a more accurate indicator of the quality of a develop process and nozzle systems. In addition, develop rate uniformity is more readily available than CD measurements, and it has less metrology-induced errors. Develop rate uniformity is calculated from resist remaining on the wafer. We used a high-resolution film thickness measurement tool (IPEC Precision Accumap 3), capable of measuring 30,000 points on a wafer, to measure film thickness.
To complement CD uniformity, we conducted a sub-develop rate uniformity test using type A resist. In this test, the resist is overexposed beyond clearing dose and develop time is reduced from its nominal value. With exposures and develop rates much above E0, the effect of the develop process is amplified compared to other module effects. We also conducted limited CD experiments with this resist to demonstrate CD uniformity improvement with the enhanced develop nozzle. For type C resist, we used a sub-E0 test because higher contrast of the resist did not allow for a sub-develop test. For this case, the resist is underexposed below the E0 clearing dose and developed using nominal puddle time.
Once the feasibility and performance improvement of the enhanced nozzle was demonstrated, we conducted extensive sub-develop tests using the enhanced develop nozzle to further optimize the developer process of record with the type B negative resist. A negative resist gives high unexposed develop rate and therefore eliminates the need for the exposure tool in characterizing the performance of the develop process. This test therefore enabled estimating the unique individual contribution of the developer module to CD uniformity and control. The IPEC Precision tool gave powerful visual images of processed wafers, aiding significantly in develop process characterization and optimization.
Further, extensive CD tests were done using the enhanced develop nozzle to characterize CD uniformity using type B and C resists on silicon oxynitride. We used an automated CD SEM to measure 250nm geometries at 30 field locations across the wafer.
Defect reduction
First, our data revealed the relationship between defect counts and rinse time and spin speed for the standard and enhanced rinse technology (Fig. 1). The defect levels are always significantly lower for the enhanced technology and depend less on rinse time and spin speed. Along with a simultaneous reduction in develop process time by 23%, the defect counts were reduced by more than a factor of two. Defect sensitivity studies also showed that the enhanced rinse nozzle resulted in wider process latitude. This demonstrates the improved mechanical rinsing effectiveness of the new rinse technology and eliminates dependence on centrifugal forces alone to transport liquid over the wafer. Also important is the fact that the enhanced rinse nozzle uniformly removes defects; however, the standard rinse nozzle has significant nonuniformity with more defects in the outer region between the 150mm and 200mm wafer diameters.
We calculated the relative impact forces on resist features of various sizes for the standard and enhanced rinse technologies. The need to reduce this impact force is the main driver in developing integrated low impact rinse and develop delivery systems. Our calculations showed that the enhanced nozzle will result in a reduced impact force by a factor of five for 180nm-to-100nm design rules compared to the standard develop nozzle and should lead to minimum pattern collapse of small resist features. Assumptions made in this calculation were a square feature size and constant flow rate for the two nozzles. Based on nozzle geometry and dimensions, calculations of differences in area covered on the wafer and radial flow distributions were performed for both nozzles. Since flow is constant, greater area of coverage results in smaller velocity, or impact force, for the enhanced nozzle.
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A new study has demonstrated a clear correlation between the smallest patternable feature size and surface contact angle [1]. The proposed pattern collapse mechanism involves aqueous solutions of the develop process penetrating the surface-resist interface and destroying the adhesion capability of the resist film. This is why it is extremely critical to minimize the impact of the fluid from both developer and rinse nozzles to improve yield by eliminating pattern collapse.
Extensive experimental flow visualizations with a new developer catch cup showed uniform flow fields and weak dependence on exhaust flow set points. The data demonstrated that there is less of a necessity for high exhaust flow to remove particles. Even at high spin speeds typically used in rinse and dry steps of a develop process, there was no backflow or recirculation in the air flow patterns.
CD control results
For the type A resist, the develop rate uniformity was 30% better for the enhanced develop nozzle (3.82%) compared to the standard develop nozzle (5.41%). The percent develop rate uniformity is the ratio of the one-sigma develop rate to the mean develop rate multiplied by 100. Our data figure clearly shows that the uniformity and range in distribution of develop rates are tighter for the new develop nozzle (Fig. 2). The mean develop rate was 450.78Å/sec for the enhanced nozzle and 431.9Å/sec for the standard nozzle. The one-sigma develop rate uniformities were 17.25Å/sec and 23.39Å/sec for the enhanced nozzle and standard nozzle.
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An improved develop rate uniformity with the enhanced develop nozzle translated into more uniform CD contours as measured by a top down CD SEM. Limited CD results showed that the within wafer CD uniformity was 25% better for the enhanced nozzle compared to thestandard develop nozzle. One-sigma within wafer CD uniformity was 4.5nm for the enhanced develop nozzle compared to 6nm of the standard develop nozzle.
Once the feasibility and performance improvement of the enhanced nozzle was demonstrated, we conducted sub-develop tests using the enhanced develop nozzle with the type B negative resist. This enabled further optimizing of the develop process of record and estimating the unique and individual performance of the develop process.
We conducted extensive CD characterization using the enhanced develop nozzle on type B resist using a 10 wafer run for 250nm grouped lines (Table 1). These results showed excellent CD uniformity and control for within wafer and wafer to wafer.
We then applied the optimized develop process of record obtained by sub-develop optimization for type B resist to the type C resist in sub E0 and rigorous CD tests on silicon oxynitride coated wafers (i.e., a 300Å CVD bottom anti-reflective coating layer). Next-generation high contrast resists like type C are the material of choice for extending 248nm DUV lithography to 100nm CDs.
In the sub-E0 test, the average develop rate uniformity was significantly better for the enhanced develop nozzle (3.5%) compared to the standard develop nozzle (8.12%). Our experiments showed outstanding CD uniformity (Fig. 3) and control within wafer and wafer to wafer (Table 2).
Conclusion
Defect reduction >2x and wider process latitude has been achieved with a simultaneous increase in throughput by reducing develop process time by 23%. These results were achieved through improved nozzle rinsing action, improved airflow around the developer catch cup chamber, and physical process parameter optimization. Such significant yield and throughput improvement translates into enhanced cost of ownership. There is an added potential of minimizing chemical and deionized water consumption to meet stringent environmental regulations.
In addition, we improved develop rate uniformity by 30% and CD uniformity by 25% for an acetal-based DUV resist and conducted extensive develop process optimization for a negative tone DUV resist; sub-develop methodology resulting in significant develop uniformity improvement. This optimized process, along with the enhanced develop nozzle, resulted in excellent within wafer and wafer-to-wafer CD uniformity and control for the negative and a type B and a DUV ESCAP-based positive resist for 250nm geometries. We are confident that our results are applicable to smaller geometries and 300mm wafers because sub-develop process optimization is a reflection of the improved mechanical distribution of the developer fluid across the wafer by the enhanced develop nozzle. Work on both these areas is currently in progress.
These uniformity improvements result from the uniform and fast coverage of the wafer provided by an enhanced develop nozzle. Such coverage is crucial during the initial moments of develop when the develop rates are very high.
Acknowledgments
An additional author is Reese Reynolds with the process technology group of Silicon Valley Group Track Systems. This project could not have been completed without the equipment level support of Bill Gendron. The process-control concepts presented here were done on the SVG ProCell photoresist processing platform and are patent pending with SVG. ProCell is a trademark of SVG.
References
- T. Zhong, et al., "Characterization of Sub-0.18µm Critical Dimension Pattern Collapse for Yield Improvement," Proc. of SPIE 1999 (submitted for publication).
- G. Mirth, "Reduction of Post Develop Residue Using Optimal Developer Chemistry and Develop
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- Khoi Phan, et al., "A Methodology for the Optimization of an i-line Lithographic Process for Defect Reduction," Proc. of SPIE, Vol. 3332, pp. 309-320, 1998.
- E.H. Bokelberg, J.L. Goetz, M.E. Pariseau, "Photocluster Defect Learning and Develop Process Optimization," Olin Interface' 96 (San Diego), pp. 127-139.
- M.S. Krishna, et al., "Reduction of Post-develop Defects and Process Times for DUV Lithography," Proc. of SPIE, (submitted for publication), 1999.
- Kevin Kemp, et al., Proc. of SPIE, Vol. 3049, p. 955, 1997.
- M.S. Krishna, et al., Proc. of SPIE, Vol. 3678, p. 1307, 1999.
Murthy Krishna is a senior process development engineer in the process technology group at the Track Division of Silicon Valley Group, 541 E. Trimble Rd., San Jose, CA 95131; ph 408/432-6807, e-mail [email protected].
Emir Gurer is the director of the process technology group at the Track Division of Silicon Valley Group.
Tom Zhong received his BS from Kunming Institute of Technology, China, his MS from California Polytechnic State University, and his PhD from the University of Arizona, all in materials science and engineering. Zhong is a senior staff process engineer at the Track Division of Silicon Valley Group.
Eddie Lee is VP of technology at the Track Division of Silicon Valley Group.
John Salois is the manager of the customer applications group at the Track Division of Silicon Valley Group.