Technology News
09/01/2000
Update on process-induced damage problems
The unwanted side effects of plasma processes and other critical steps in the wafer fab require more attention as demands on device performance increase. What used to be minor effects are now significant challenges as, for example, gate oxide thickness decreases. The latest work in this field was presented at the 5th International Symposium on Plasma Process-Induced Damage held in May in Santa Clara, CA.
 The antenna circuit model for a) bulk-Si technology and b) SOI technology. (Source: The American Vacuum Society's 5th Int'l Symposium on Plasma Process-Induced Damage) |
Oxide scaling was one of the areas of most concern in current research. Experiments by P.W. Mason et al. of Lucent Technologies, Orlando, FL, showed that the severity of plasma damage increased as the gate oxide thickness was decreased from 115Å to 55Å. The main damage source was the RF backsputter via clean process that was used to prepare vias for metal deposition. They found that the plasma damage correlated with yield loss as well as long-term reliability degradation, although, interestingly, not with short-term reliability problems. The situation was summarized well: "As reliability margin of gate-oxide shrinks with technology scaling, the impact of plasma charging damage on gate-oxide long-term reliability becomes more severe. The need to adequately address the plasma charging damage problem increases."
Another paper from Lucent (by Kin P. Cheung et al.) offered no reason to believe that these challenges would be solved anytime soon. They looked at techniques for measuring plasma charging damage in ultra-thin gate oxides and found that both Vt shifts and current leakage are not capable of providing adequate sensitivity. If test structures are en-larged, direct tunneling current will overwhelm soft breakdown conduction. Small test structures are not the answer, though, because they are not sufficiently sensitive to determine whether yield- or reliability-degrading damage has occurred. In short, the measurement techniques currently available cannot determine whether or not a low level of plasma-induced damage is occurring.
More encouraging news was heard about the resistance of silicon-on-insulator (SOI) devices to plasma charging damage. A circuit-based model by Terence Hook et al. of IBM Microelectronics, Essex Junction, VT, compared devices built on bulk Si and SOI substrates. The models are shown in the figure, and make it clear that the main difference is that all of the nodes in the SOI model are independent of the substrate because of the continuous oxide layer.
This prevents current flow through the substrate, and other work presented by IBM (A. Bryant et al.) also showed that lateral current flow is suppressed. This subtle but significant benefit of SOI should become better understood and appreciated as the volume production of SOI continues to increase. — J.D.
(For more coverage, see "Process-induced damage in Cu and low-k dielectrics," on p.28.)
Industry-leading flip-chip PBGA package
Motorola has demonstrated an industry-leading flip chip plastic ball grid array (FC-PBGA) package capable of routing hundreds of inputs and outputs (I/Os) from a die with array pitches as low as 150mm. The fine pitch capability is designed to enable smaller die sizes, more direct interconnect, and faster operation for devices such as next-generation microprocessors.
Simon Thomas, VP and director of Interconnect Systems Laboratory for Motorola's Semiconductor Products Sector, says, "The reduction of die pad pitch from today's state-of-the-industry 225mm down to 150mm enables significant performance increases in advanced CMOS devices, as much as 100 MHz faster speeds for microprocessors. The package technology we have demonstrated contains more than 800 die to package interconnects and has met all our performance and reliability goals to date."
The 150mm pitch FC-PBGA requires advances in four technology areas including fine pitch wafer bumping, advanced high density interconnect (HDI) substrates, automated test and inspection, and fine pitch assembly. Through internal development and collaboration with key suppliers, Motorola has combined the capabilities of the four areas. Reductions in die size and interconnect length made possible by the fine pitch capability directly translate to device performance and cost advantages.
For I/O intensive devices that may be pad limited at current pitches, moving to 150mm pitch may provide a more than 250% increase in I/O density. Lower operating power is also possible. In addition to the performance and cost benefits, portable products can profit from the smaller form factor of the fine pitch package. Currently in the development stage, this packaging technology is expected to be available for Motorola's future advanced CMOS products. — P.B.
Role of e-connectivity applied to wafer fabs debated
Remove "300mm" from exhibits at Semicon West 2000 and the overwhelming buzzword was "e-connectivity." Looking back from the future, we may remember Semi West 2000 as the milestone year for Internet-based solutions applied to semiconductor manufacturing technology.
Yet, at the show, opinions varied widely on how the Internet will best be applied to processing equipment and materials supply and operation, as heard from a select group of supplier CEOs, speaking to the press from a panel organized by San Francisco's public relations firm, The Loomis Group.
On the pro side, Michael Parodi, chairman and CEO at Tegal, said, "It certainly is going to help supply chain management. From my perspective, it's all about reducing time to market and collapsing lead times. If you have very short lead times and you have a supply chain that's tightly linked, then you're going to benefit from it." Parodi did caution that an e-business environment involves inserting yet another communication factor between the customer and the OEM. "This can be a confusion that is going to require some working through," he said.
From another view, Brad Mattson, CEO, Mattson Technology, said, "Despite the fact that I see Intel promoting it and it's 'en vogue' to talk about, it's really questionable how applicable it can be. You have 20 companies in the industry that account for 80% of the equipment purchased and 10 equipment companies that account for 70% of all the equipment sold. E-business is not designed for 10 or even 20 companies that all have incredible communication links already. So it's probably not going to be as mainstream as it would be in some areas [industries]." Mattson does see, perhaps, a role for e-connectivity for equipment support. "When you have 5000 or 10,000 systems in the field with thousands of people in the support network, maybe there will be connectivity. But, and this is a key point, customers have to allow you to connect to their tools and have access to that information. They could become their own worst enemy at that point."
The right kind of fab access to data could lead to knowledge that would benefit the industry. Doug Schatz, chairman and CEO of Advanced Energy, said, "Right now we can't get access to subsystems on customers' tools, so they can't get access to some valuable information." Schatz foresees much of the increase in tool productivity that the industry craves, "the ability to improve their design and the knowledge of how they operate, coming through web connectivity (not e-business)," he says. To really make dramatic improvements going forward, IC manufacturers need to get access to data that enables real understanding and change to the underlying behavior of tool subsystems, the components, and how these all operates together.
The argument be-hind Intel's endorsement of Internet structures was that it is already a supply-chain management company with a very structured system that can easily adapt to the Internet.
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"Everybody's intellectual property becomes everybody else's. I think that's going to be the 'nub' of this whole issue that's going to be very difficult to overcome." — Michael Parodi, CEO, Tegal
Clearly, panel members related the technology and business advantages, or not, of Internet connectivity to a given business. Tony Khouri, president and CEO of Rodel, said, "If you're in transaction business, e-business is going to be a fantastic value addition. If you're in supply chain and the value of moving a product is more information than the product itself, it can add a lot a value. But if you're technology or knowledge based, the value will be limited. With semiconductor manufacturing, there is a lot of knowledge-based interaction that has to happen between scientists and engineers."
It seems that much of the concern over e-connectivity strikes at the heart of semiconductor manufacturing itself. Parodi said, "[The kind of data and knowledge concept being discussed] moves toward a model that takes away differentiation, driving toward a commodity business. Everybody's intellectual property becomes everybody else's. I think that's going to be the 'nub' of this whole issue that's going to be very difficult to overcome." Schatz countered, "That's the fear, but humans will find a way to make sure their fears are totally protected. We still have to make progress."
Don Mitchell, president and CEO at FSI International, said, "Remote diagnostics, for example, is going to be a required subsystem for every piece of capital equipment in modern 300mm fabs. But there are a number of customers, despite their request to have this, that won't allow you access to it. We will have to go through a learning period before that access is given; we will need to provide a firewall system." Panel participants agreed on the need for firewall protection, perhaps standardized, for both suppliers and users. Mitchell's emphasis, however, was, "On our way there, whoever has access, wins. So it's the first that gets access to this data that has a competitive advantage over the rest of the field. It's very important that we understand where this gets you. The people that get the access first will have a competitive advantage and will continue to promote that model. It will add value to the industry. It will add value to the suppliers as well as the end customers."
Schatz added, "It's such a dynamic. As soon as somebody has the competitive advantage, they take advantage of it and the performance of the tools changes and engineers can do more with it. And so, the game picks up its pace. Only those that will be involved [with e-connectivity] will be prepared to play. I think it really will create a discontinuity."
Ken Smith, CEO of netMercury, sees third-party providers playing a role in establishing e-connectivity trust. "On the supply chain management side, customers are telling us they are willing to share information, but with a limited amount of people, often not OEMs."
Consider Applied Materials, noted Mattson. "How is it that the largest company in the industry by far is also the largest growing company in the industry? They have preferred information. They know more than anybody else about what's going on. They have more access to data than anyone so they more easily meet and satisfy their customers needs. There is a lot of power in that." — P.B.
FSI, Dow team up on low-k process
FSI International, Chaska, MN, a maker of processing equipment for manufacturing microelectronics, has teamed with Dow Chemical, Midland, MI, to jointly develop a process for 0.13mm technology.
Under the agreement, the companies will use equipment from FSI and low-k dielectric resins developed by Dow to create a fully integrated dual damascene process. The process will use Dow's SiLK resins and copper circuit lines using a spin-on dielectric system from FSI. IBM, Armonk, NY, said in April that it is committed to spin-on dielectric technology for dual damascene processing. Other industry suppliers will also be involved in the work.
Initial work will focus on 200mm tools and processes, but will move to a 300mm platform "in the near future," the companies said. Dow developed the resin under an Advanced Technology Program grant from the National Institute of Standards and Technology (NIST). The resin is intended as an interlayer dielectric material for high-performance integrated circuits, to act as an insulator for the ever-denser interconnects packed onto chips and cut down on electrical cross-talk. The SiLK resin, in combination with high-speed copper interconnects, allows electrical signals to propagate 37% faster than conventional technologies and uses less power.
"Pooling our technical resources with FSI will help us support our customers' effort to integrate SiLK resin into their copper damascene process flows at the 0.13mm node, as well as future device generations," said Joe Carr, GM of Dow Advanced Electronic Materials, in a prepared statement.
The FSI equipment allows spin-on processing for 180nm and 130nm technology. The resins have a dielectric constant of 2.65 for both copper dual-damascene processing and aluminum/tungsten gapfill technologies and are stable up to 450°C. They are compatible with CVD or electroplated copper and have an etch selectivity ratio greater than 20:1 vs. hardmask.
Dow's NIST-sponsored program is aiming to create materials with an "ultra-low" dielectric constant of 1.5 for future generations of circuits with even smaller feature sizes. The $17 million project is slated to run into 2002. — Neil Savage, Contributing Editor
Process-induced damage in Cu and low-k dielectrics
Calvin Gabriel, Advanced Micro Devices
Most of the low-k dielectrics being considered as replacements for traditional intermetal oxides are very susceptible to damage in plasmas. Here the concern is focused on the chemical and physical effects of the plasma rather than on charging damage. Ching-Fa Yeh et al. of the National Chiao Tung University, Hsinchu, Taiwan, found that O2-plasma ashing after via etch through methylsilsesquioxane (MSQ) caused k to increase from 2.7 to a worse-than-oxide 7. Insulating properties of the MSQ were also degraded. Damage can be avoided at a cost by capping the low-k sidewalls before ashing using selective liquid phase FSG deposition. The structure is shown in the figure.
Anthony K. Stamper et al. of IBM Microelectronics, Essex Junction, VT, reported seeing charging damage issues during damascene processing from several sources: 1) via etch, 2) CMP and post cleaning, and 3) PECVD of dielectrics.
Charging from CMP is not normally expected because of the lack of a plasma. However, damage may result from friction-generated electrostatic charge during Cu CMP, and a stage is reached where islands of metal can collect charge much like during metal etching. For the case of a via-first trench-last integration scheme, trench etching is an additional potential damage source.
When ashing dual damascene structures, Shawming Ma et al. of the Dielectric Etch Division of Applied Materials, Sunnyvale, CA, presented two main damage concerns. The first concern is charging damage from the long ash, with high aspect ratios contributing to electron shading, and the second is physical damage, such as barrier attack, bowing of low-k materials, and faceting of the dielectric or its hard mask. High power ashing was found to increase charging damage, while a low power directional ash with oxygen plasma was found to address all of the above concerns.
Around the 0.1mm technology node, metal gates might replace poly gates to avoid the poly depletion effect and reduce gate resistance. Metal gates, however, raise other concerns such as process compatibility, metal penetration, and Vth variation and adjustment. C-C. Chen et al. of National Chiao Tung University plus collaborators from National Nano Device Laboratories, Hsinchu, Taiwan, and TSMC, Hsinchu, Taiwan, studied TiN metal gate capacitors and found severe charging damage from the additional plasma processing needed to integrate metal gates. N2 plasma post-treatment suppressed the gate leakage current.