Semi West explodes with new products and ideas
09/01/2000
A special report by the editors of Solid State Technology, Microlithography World, and WaferNews
 ASM's new RTP tool, the Levitor 4000. |
The extremely sunny skies at Semicon West '00 matched the upbeat, optimistic mood of attendees. With the booming economy and strong industry sales, new mergers and products seemed to be announced at every show booth. The aisles were jam-packed with those who were curious and those who had money to spend. The vast majority of exhibiting companies were experiencing a high they haven't had in years. Under this layer of joy, there was little apparent worry — on the show floor, at least — about what would come next. In the back rooms of the technical program hotels, however, the new Roadmap guidelines and 300mm issues were causing concern and disagreement about the future, even as participants presented potential and actual technological breakthroughs.
Deposition technologies address ITRS issues
Some serious science and engineering — and some showmanship — were in evidence in the deposition process area of Semicon West. NuTool Inc. (Milpitas, CA) had one of the most interesting new tools to discuss at the show. The start-up, headed by Applied Materials alumnus Homayoun Talieh, has figured out a way to plate and polish copper simultaneously, allowing for some impressive results with trenches and open areas being metallized to the same height (see figure). This process, which NuTool has dubbed electrochemical-mechanical deposition (ECMD), could conceivably eliminate CMP. Even if it falls short of that goal, it could still greatly reduce and simplify the CMP step. Talieh said that a tool is in beta-test at Micron, and that NuTool has one P.O. in hand with two others to follow shortly from top-five semiconductor manufacturers, including a foundry and two IDMs. Talieh didn't provide many process details, but NuTool's low profile will end with an introduction scheduled for Semicon Japan in December.
Some of the red boxes of the ITRS99 roadmap might be turning yellow soon with recent advances in atomic layer deposition (ALD). ALD has been seen as the solution for many of the scaling-related challenges on the roadmap, and Tom Seidel, CTO of Genus Inc., Sunnyvale, CA, claimed that ALD is now cost-competitive with high-end CVD. The Genus ALD system is part of the Lynx2 cluster tool, allowing IC makers to avoid an entirely new tool just for ALD development. The new capabilities announced by Seidel include Al2O3 and Ta2O5 films for memory capacitors and gate stacks. These dielectrics feature thermal stability improvements due to an alloying capability. Genus has developed a process that can control for any ratio of Al to Ta by depositing a specified number of layers of one oxide and then the other. The company has demonstrated 100% step coverage in 30:1 aspect ratio structures and at 0.1mm features. The Al2O3 film shows a five order of magnitude improvement in gate leakage compared to SiO2 with an equivalent oxide thickness of 2nm.
Some of the advanced deposition technologies at Semicon were based on more established processes. Trikon Technologies, Newport, UK, for example, introduced an ionized physical vapor deposition (i-PVD) module that extends the use of all-PVD liner solutions to sub-150nm design rules. Good base and sidewall coverage with Ti and TiN is possible because the ionized process increases the energy and directionality of the metal species arriving at the wafer. The deposited material is also denser because of the ionized process. Trikon claims that this technology provides a significant cost advantage over CVD for liner deposition.
After the dry ice and Dom Perignon settled, Novellus had some interesting updates on its low-k dielectric solution. The company announced VECTOR, its new PECVD system, touting breakthroughs in low-k processing. The key process is a sandwich of SiC/Coral/SiC for dual damascene structures. Coral's dielectric constant is 2.7, with a resulting effective dielectric constant of 3.0 for the stack. Other materials can provide these values, but Rick Hill, CEO of Novellus, claimed that it has an order of magnitude better structural integrity, making it the most manufacturable and reliable low-k material. Hill said that the 300mm VECTOR tool is lower in cost than a comparable 200mm tool, making it significantly ahead of the Roadmap target of a 1.3x cost for 300mm vs. 200mm. Hill also noted its streamlined design with 40% fewer components, 40% smaller footprint, and a throughput of 120wph. The Coral process on the VECTOR tool has been validated at UMC with 256k SRAM chips, showing 37% less line-to-line capacitance compared to FSG and SiN. A dozen other manufacturers are in the prototype phase as well.
Integrated metrology moving beyond buzzword status
Discussion of integrated metrology was everywhere at Semicon, of course, and there were actual examples of it, too. Semitool, Kalispell, MT, introduced its Paragon copper electrochemical deposition (ECD) tool; inside it is a nondestructive thin-film metrology system from Philips Analytical, Almelo, The Netherlands. The Philips Analytical system uses an opto-acoustic technology that inspects the incoming Cu seed layer and the Cu ECD layer, permitting the ECD process to be optimized using a closed-loop feedback process. This works because Semitool's Paragon system can adjust the uniformity of the Cu layer, and because of the speed of the metrology system. This real-time interaction of metrology and the process is true integrated metrology, not just a metrology system that is merely physically attached to the process equipment. It is also an example of the emergence of Cu creating new opportunities in the metrology field, because the opto-acoustic method works only with heavier atoms, such as copper, but not aluminum.
Nova Measuring Instruments, Rehov-oth, Israel, introduced an integrated met-rology capability for overlay registration, marking the third process area that the company has entered, beginning with integrated CMP metrology and followed by CVD. Giora Dishon, president and CEO at Nova, had some interesting comments, saying that even though integrated metrology is widely accepted as a critical capability for continued process advancements, it is still a very tricky business because of ownership issues. With a metrology system truly integrated into a processing tool, it needs to be very clear who gets the call when something goes wrong. This could foster some interesting alliances (and battles) as integrated metrology continues to grow. Dishon also likes to characterize integrated metrology as "single-wafer process control," as opposed to the traditional "batch" process control where many wafers are run through a process and then evaluated. The cost benefits of evaluating one wafer at a time before processing many more would be significant, as long as the impact on throughput is close to zero.
Single-wafer thermal processing
Thermal processing is another area where the single-wafer approach was being promoted. ASM, Bilthoven, The Netherlands, introduced the Levitor 4000, a new RTP tool in which the wafer sits 0.1mm away from heating blocks above and below it (see photo on p. 34). With such a narrow spacing, conduction through the N2 ambient dominates the heat transfer, making ramp rates of 300°C/sec possible. Since the heating rate is strongly dependent on the distance between the heating sources and the wafer, ASM developed a "gas-bearing" method in which nitrogen flowing upward and downward holds the wafer perfectly level between the heating elements. They even claim that it will temporarily flatten any bowing of the wafer during the process.
Silicon Valley Group, Scotts Valley, CA, also introduced a single-wafer RTP tool, emphasizing its low cost of ownership, temperature control, and oxide quality compared to lamp-based systems. SVG's tool, Xcelerate, consumes significantly less power than lamp systems, and the system's hot wall isothermal chamber eliminates emissivity effects. The chamber is also made of quartz, which, unlike stainless steel, allows Cl oxidations and Cl cleans, processes that improve oxide quality.
That ubiquitous prefix
"e-Diagnostics" was one concept that was mentioned more than once in the Moscone Convention Center in July, and Varian Semiconductor Equipment Associates, Gloucester, MA, had something real to present. They introduced a program called "vCare" — tastefully avoiding the "e" prefix — in which they can monitor their customers' equipment remotely, allowing them to assist more quickly with any problems that arise or help to prevent them.
Richard Aurelio, president and CEO of VSEA, said that the system can monitor more than 5000 data points every 50 msec, an astonishing quantity of data. They can do this, though, only when their customers allow it, so initial security and confidentiality concerns are being addressed. There are still likely to be security issues that arise as IC manufacturers share real-time fab data with their equipment suppliers, so this will be an interesting area to watch. VSEA is a likely leader of the field because of the complexity of its ion implant and plasma doping systems. The company introduced VIISta 10 P2LAD, the latest generation of pulsed plasma doping tools. The ultra-low energy system allows 100Å junction depths, an ITRS necessity at the 70nm node.
Backend metrology matures
The continuing convergence between frontend and backend equipment was evident in the metrology area at the San Jose end of Semicon West. The specific functions might not be merging soon, but the approaches to the varied challenges look increasingly similar.
Applied Precision, Issaquah, WA, introduced its waferWoRx probing process analysis system at the show, revealing that it is in the alpha-test phase at Agilent's production line, Ft. Collins, CO. The waferWoRx system evaluates the probing process by characterizing each probe mark with 40 parameters identified by advanced image analysis software. By combining data from the prober, probe card and probe card analyzer, it is possible to implement corrective actions to the probing process. This can increase the prober's uptime, for example, by identifying when the probe card needs to be cleaned. Current practice often specifies cleaning at regular intervals, whether or not it is necessary. The graphical representation of the system's output looks very much like overlay metrology toward the frontend of the wafer fab.
 Keithley Model S633, an automated parametric test solution for 300mm wafers with Cu/low-k interconnects. |
Keithley, Cleveland, OH, introduced two new systems for semiconductor characterization. Its Model 4200-SCS semiconductor characterization system has an instrument structure that allows simultaneous measurement of eight different channels, and it also offers 0.1fA current measurement resolution, which the company claims is an order of magnitude better than the closest competition. A key to this capability is a mobile, low-noise pre-amp that mounts directly on the probe station to eliminate interconnect noise and cable parasitics. The equipment offers standard, curve trace applications, and is designed for infrequent, nonexpert users. Keithley also introduced the S633, an automated parametric test solution for 300mm wafers with Cu/low-k interconnects (see photo). Process anomalies associated with new interconnect materials require different monitoring schemes, and Keithley says that its tool can handle linewidth variations introduced by CMP, barrier layers, barrier cracks and pinholes, the low capacitance of low-k dielectrics, and the difficulties of verifying probe-to-pad contact with Cu pads.
Robotic Vision Systems Inc. (RVSI), Canton, MA, was showing its WS-2000 wafer inspection system and LS-7700 component inspection system. The WS-2000 performs both 2-D measurements with an optical system and 3-D measurements with a laser system. The integration of both types of measuring capabilities provides the flexibility to maximize throughput. Michael Gray, VP of sales and marketing for RVSI, says, "The WS-2000 is the only production bump inspection system with enough resolution" for current bumped wafer metrology requirements. The LS-7700 uses RVSI's MicroMap laser-scanning technique for complete package inspection of leaded, grid array, and now leadless packages such as LCCs, BCCs, and QFNs.
Lithography tools for 300mm
Also discussed at the show was the switch to 300mm wafers, which poses unique challenges for the makers of lithographic exposure tools: Customers want the new tools to make the same number of 300mm wafers as were produced by recent 200mm systems. Most fab equipment operates on all the die on a wafer at once. Not so the lithography scanners and steppers, which expose each individual field and then step to the next one. Since there are 2 1/4 times more fields on a 300mm wafer, it really could take twice as long to expose one. Achieving the desired 300mm throughput requires the wafer and reticle stages to move further and faster, while the overlay and resolution demands of <130nm imaging reduce the tolerable errors and vibrations. All of the exposure tool manufacturers announced new products or platforms for this purpose.
Silicon Valley Group Inc. announced the Micrascan IV and V systems, which incorporate an innovative low-mass precision wafer stage, without interferometer retroreflector mirrors. The interferometer systems of the Micrascan IV and V are inside out compared to previous designs, with the mirrors on the frame and the laser-beam-launching and collection optics on the vertically oriented stages. The lightweight ceramic stages allow increased servo bandwidth and scan speeds above 300mm/sec. The reticle stage, however, must move 4x faster. The quick, four-wavelength HPAS alignment system has a 1s overlay accuracy of 3nm, according to Peter Convertito, director of strategic marketing at SVGL. With large numerical aperture (0.75) catadioptric projection lenses, the 193nm Micrascan V tools are designed to expose 130nm CDs with standard mask illumination and 100nm half-pitch using resolution enhancement technologies (Fig. 4). The 248nm Micrascan IVs, with NA = 0.60 optics, are intended for noncritical applications.
ASML chose an entirely different approach for its gigantic new "Twinscan" platform, intended for operation both at 200mm and 300mm. David Chavoustie announced three new tools based on this new platform with the 248nm 0.70NA AT-700 coming first, followed by an i-line tool (AT-400) and a 0.75NA 193nm tool intended for production, the AT-1100. A contemplated 157nm system and an even larger-NA 248nm scanner will be compatible. To allow rapid acceleration of the relatively heavy wafer stages, ASML uses a "free-reaction mass" concept in which the linear stage motors push against a countermass, which moves in the opposite direction, rather than against the fixed scanner frame. Since the countermass is free to move, it absorbs the impulse from the acceleration without inducing vibrations in the exposure tool structure. The center of gravity remains fixed, eliminating gravitational torques. The stages accelerate and decelerate according to Newton's third law, just like a rocket in vacuum, which spews reaction mass behind it.
According to ASML, the new system reduces moving average alignment error to 3nm and moving standard deviation (vibrational) distortions to <2nm, a 10-fold improvement. However, the Twinscan systems will not achieve 120, 300mm wph throughput in one step; rather, the initial tools will be specced for 62wph, with throughput doubling by 2002, according to Jim Greeneich. Achieving full potential of the Twinscan platform, with the enormous granite slab beneath the lone wafer stage, will evidently require more development.
Canon chose a more conservative approach, introducing an "experienced" 200/300mm tool set comprising a high-NA KrF scanner, an ArF scanner and an i-line stepper for noncritical work, with a field size matching the 26mm x 33mm scanner field. All are designed for high throughput — 88, 300mm wph for the scanners and 100 for the stepper. The matched fields allow a mix-and-match strategy with the lowest CoO tool applied to each level. While Canon did not reveal its stage design, countermasses and improved aerodynamics allow 350mm wafer speeds with overlay accuracy below 23nm. Highly efficient illuminators and high power sources (a 4kHz ArF excimer laser for the FPA-5000AS2 and a 4.5kW Hg lamp for the FPA-5500iZ) also contribute to the throughput. Canon expects to begin shipping the FPA-5000ES3 KrF system in the second half of this year, with the AS2 following early in 2001, according to Phil Ware, director of US semiconductor marketing. Ware claimed that the CoO of the new ArF tool is a factor of 3 lower than the first generation tools, making production feasible. Looking toward the future, Ware predicted that a 0.85NA ArF tool with a 22 x 26mm field and 5x magnification would prove the most economical solution between the 100nm and 70nm nodes. Strong resolution enhancement technology will be needed to achieve a 70nm half pitch with that or any foreseeable optical system.
Chris Sparkes of Nikon pointed out that Nikon has had 300mm-capable KrF scanners in the field since the NSR-S203B, and the newly introduced 0.75NA NSR-S205C promises >83wph for wafers of that diameter along with 130nm resolution (using RET) and <30nm overlay. To facilitate double-exposure RETs, the quick reticle change system characterizes the mask on its first use and remembers the proper settings on later exposures. Nikon plans to ship 100 of these systems in FY00, according to Sparkes, out of 400 total exposure tools. Anticipating further business in 2001, Nikon is ramping production capacity toward its former record of 600 tools/year. The 300mm-capable NSR-SF100 i-line scanner also matches the 25 x 33mm field of the excimer scanners for mix-and-match applications. A new 0.68NA ArF exposure tool is promised for early 2001. Beyond that, Nikon would only admit to "narrowing options" for 157nm designs until customer needs develop. Nikon has internal sources of CaF2 and could develop other optical materials if necessary.
The switch to 300mm will create problems and opportunities for other parties in the lithography food chain. For example, most wafer bumping for packaging is done using mask aligners on 200mm and smaller wafers. Karl Suss is only now beginning to address challenges posed by larger, heavier, and more warped 300mm wafers. Elmar Cullman, principal scientist of Karl Suss, reports customers also want full-field aligners for 300mm with >80wph throughput. He predicts such a tool will be available next year with a 13-in. mask and a temperature-controlled chuck to limit misregistration.
In the mean time, Ultratech Stepper is trying to replace mask aligners in wafer-bumping applications with its Saturn Spectrum 300 1X stepper, the first of which has just shipped. With broadband optics, the Spectrum 300 is expected to produce 60, 300mm wph, but can also print other wafer sizes due to its extremely flexible machine vision and wafer-handling systems.
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RIGHT. Andy Johnson, VP of sales and marketing, Lithography Div, FSI
"For track-makers, 300mm is a new ball game," reports Ardy Johnson, VP of sales and marketing in the Microlithography Division of FSI. "It gives us an opportunity to differentiate our products with in situ metrology and feedback control." Johnson reported that the FSI tracks already have a 90wph throughput for 300mm wafer processes and he hopes to drive that to 110wph within the year. Because customers want the option of running all wafer levels on every cluster, and some masking levels use inorganic ARCs deposited elsewhere, up-to-date tracks must be able to change parameters quickly, including bake temperatures, between lots.
R&D for future generations
Fluorine laser sources at 157nm now appear likely for the litho tools that follow the ArF generation at 193nm, but keeping up with the ITRS Roadmap will require a dramatic acceleration of resist development, among other things, according to Luc Van den hove, head of micropatterning at IMEC in Leuven, Belgium. IMEC hopes to play its part by installing a mid-field 157nm exposure tool in a complete N2-purged litho cell with which to begin resist testing in mid-2001. By 2003, there should be a full-field, production-capable 157nm prototype available to the IMEC consortium, according to Van den hove. The 157nm collaboration would be modeled on the very successful 193nm program currently running at IMEC with an ASML PAS5500/900 exposure tool.
The need to invest $30-40 million/year to keep up with laser source R&D in this era of rapid wavelength changes induced Komatsu Ltd., which claims 15-20% of the lithography excimer market, to create a joint venture with USHIO Inc., which sells and supports other light sources. The new company will be called Gigaphoton Inc., with headquarters at the Asahi Tokai building in Tokyo and major R&D centers at Hiratsuka and Oyama. Gigaphoton grew out of an ASET-backed collaboration on F2 lasers between the two companies. Gigaphoton will take over the G40A ArF laser product, which incorporates a unique gas technology and produces 20W of pulse-stretched power. The technology Roadmap anticipates reducing the linewidth of this source to 0.3pm to support large-NA scanner lenses by 2002, with F2 lasers following.
Speaking at the FSI lithography breakfast, C. Grant Willson of the University of Texas, Austin, decried the exponential increase in exposure tool costs. Seeking an optics-free paradigm, Willson proposed "step, slurp, and flash" in which a transparent stamper would be placed very near a planarized substrate and a photopolymerizable liquid would flow between by capillary action, filling grooves and gaps. Ultraviolet exposure would convert the liquid to a resilient solid at which point the stamper would be removed. Using templates fabricated by commercial photomask companies, Willson's students have already demonstrated 80nm resolution and, perhaps more important, that the templates are self-cleaning.
Sub-half-wavelength device fabrication requires detailed understanding of many processes and their interactions as well as practical measurement and calibration procedures. In an attempt to relate measurement science to real-world metrology and lithography, Jim Potzick of NIST chaired a meeting of the Neolithography Consortium on July 10. The purpose of the consortium was to fulfill the predictive potential of process simulation by encouraging software compatibility and parametric anchoring to metrology. Andreas Vladar, also of NIST, observed that no meaningful metrology was possible without simulation. Nevertheless, the Neo-lithography Consortium is likely to be stillborn unless companies involved in metrology, lithography, and simulation lend more support than was evident at the meeting.
For the first time, lithography experts at Semicon seem to have conceded that optical methods will be used below 100nm half-pitch, although the exact illumination wavelength and technology remains debatable. Whether or not some advanced 193nm tool or early 157nm system begins production at 70nm half-pitch, strong resolution enhancement technologies that place major constraints on chip design will prove essential. No lithography hardware can be acceptably productive in this regime without help from design and simulation software. The $7 billion/year litho-tool industry with its $2 billion/year leading-edge market is driven along the ITRS Roadmap by surging demand, but the paradigm is already shifting away from PCs and toward consumer products, where time-to-market is more important than marginal technology improvements. The R&D agendas will change to accommodate these emerging realities. Semicon 2000 may be the last one dominated by such hardware innovations as the move to 300mm wafers.
Will tool sales go South in Octboer '02?
A panel of chief executives at Semicon West got off to a rousing start when Eric Ross, an analyst for Thomas Weisel Partners, presented a dramatic chart showing robust growth in the process tool market up to October 2002, at which time everything drops like a rock.
The reason, explained Ross, is "...that at least a dozen superproductivity fabs will come on stream, and it will end this cycle." Chip oversupply would lead to a huge slump starting in late 2002 and going through 2003, he contended.
Several of the assembled CEOs chimed in to agree with his upbeat forecast for the next two years, but they strongly disagreed that everything will fall apart in late 2002. "We expect the upturn to last longer than two years," said Tony Khouri, president and CEO of Rodel. Don Mitchell, president and CEO of FSI International added: "Our customers don't see a downturn for the next two years; they don't see any reason why there should be one."
Mitchell pointed out that the semiconductor content of PCs, which has driven the chip industry in the past, is about 20%, while the content of Web-linked appliances, PDAs, and similar portable devices is about 50%. Michael Parodi, CEO of Tegal, said that his company sees a steady boom ahead in wireless telecommunications.
"About 50% of the capital spending in the US now goes into IT infrastructure," pointed out Scott Gehlke, president and CEO of Ion Systems, "and the US is way ahead of the rest of the world." As a result, he contended, the buildup should stretch out as the rest of the world follows.
There is a great variety in the demand for chips, with tremendous growth in many sectors, according to Douglas Schatz, chairman and CEO of Advanced Energy. He sees a continuous buildup ahead. Mitchell of FSI agreed that customers were seeing a wider variety in demand, but he does not feel that they are getting better at forecasting.
"Forecasting on the demand side is not too bad," commented Brad Mattson, CEO of Mattson Technology, "but Semi needs to do something about supply forecasting."
"Demand changes a lot faster than brick and mortar can meet it," according to Khouri of Rodel. FSI's Mitchell pointed out that we are always looking at the wake of the boat, and we need to find a way to look through the windshield.
The emergence of "superproductivity fabs" appears to hinge on the ability of chipmakers to bring 300mm process tools up to yield fairly rapidly. The panel was asked if this appears likely.
Looking back at ancient history, Mattson said that it had taken eight years to bring 16K DRAMs up to yield. He expects that learning curves will be much steeper for 300mm.
"We can expect much better tools for 300mm," Mattson added. "That's what Infineon found."
Customers are asking for bridge tools (easily convertible from 200mm to 300mm wafers) according to Mitchell of FSI. They can learn processes on these tools and then convert, he said. Chipmakers are pushing hard to reduce cycle times, according to Mattson, and Mitchell suggested that they may insist on a 30% reduction in cycle times with 300mm tools.
While all this suggested that a new generation of superproductivity fabs may indeed be in the offing, executives were much less sanguine about this conclusion in discussions later. The conversion to 300mm wafers will coincide with the shift to 0.13mm features, the integration of copper and low-k dielectrics, and extensive use of reticle enhancement techniques. Taken all together, these could stretch out the learning curve, many of them felt.