What is the future of sub-100nm CMOS: Ultrashallow junctions or ultrathin SOI?

09/01/2000

M.I. Current, S.W. Bedell, I.J. Malik, L.M. Feng, F.J. Henley, Silicon Genesis Corp., Campbell, California

overview

Planar CMOS transistors on bulk silicon wafers are expected to reach their limits at gate sizes of about 50nm in 2005-06. Many of the process and materials constraints that combine to force this changein technology path are relaxed or removed for CMOS devices fabricated on SOI wafers. This article outlines the principal issues limiting junction formation for sub-100nm CMOS on bulk silicon and presents an alternative roadmap using SOI wafers. An SOI wafer fabrication technology is described that provides a room temperature, atomic layer cleaving process with unprecedented levels of control on silicon layer thickness, as well as a clear path for extension towards the ultrathin SOI regime.

SiGen atomic layer cleaving tool for room-temperature separation of donor and SOI wafers. Courtesy Tom Tracy Photography, San FranciscoClick here to enlarge image

The International Technology Roadmap for Semiconductors (ITRS99) documents a clear "end of roadmap" event horizon at the onset of IC device scaling to 50nm gate lengths, anticipated in 2005-06 [1]. The premise of the ITRS99 study was to predict, as far as possible, the characteristics of an extension of the industry's dominant "standard technology," planar CMOS transistors fabricated on bulk silicon wafers. At the end of the near-term view of ITRS99, anticipated between 2005 and 2008, nearly all of the 30 or so transistor characteristics required for the extension of high-performance IC devices to meet the expectations of Moore's Law are listed as "no known solutions." This is a clear signal that IC transistor technology requires fundamental changes in the next half-decade.

Many of the challenges for CMOS transistors in bulk silicon are relaxed or removed when "silicon-on-insulator" (SOI) wafers are used. A good example is the control of shallow source/drain (S/D) junction depths. In bulk silicon, obtaining shallow junctions requires careful control of thermal budgets, with the use of rapid thermal annealing "spikes" or laser annealing, to limit both vertical and lateral dopant diffusion while obtaining high dopant activation and adequate defect annealing. With fully-depleted, thin-SOI, the S/D junction depth is determined by the Si-SOI layer thickness. The process challenges shift to controlling lateral diffusion and obtaining abrupt lateral junction interfaces.

Limitations for ultrashallow junctions in bulk silicon CMOS

The principal challenges for CMOS shallow junctions are:

1) limiting dopant diffusion to shallow depths,
2) activating dopants for low resistivity junctions, and
3) obtaining highly abrupt lateral and vertical junctions.

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The ITRS99 values for these key transistor parameters are listed in Table 1.

Figure 1. Sheet resistance and junction depths for low-energy boron implants and spike-RTP anneals [8] and industry expectations for S/D extension junctions [1] (starting with 140nm gates to 22nm gates at the head of the arrows) for cost-focus and performance-focus devices. The dopant resistivity for sub-keV boron implant and spike-RTP process (in CZ-Si) is limited by a "wall" at about 10^-3Omega-cm.

Junction scaling. To maintain "proportional scaling" for CMOS for sub-100nm gates, S/D extension junctions should shrink according to a design rule of X_j (extension) approximately equal to 0.4 x L_gate within a range of ±25%. Controlling junction depths to less than 40nm for sub-100nm gate transistors will push the limits of sub-keV boron implantation and "spike" anneals [2].

Figure 2. Si and buried oxide (BOX) layer thickness for various device types of SOI wafers.Click here to enlarge image

Dopant activation. The expectation for dopant activation in the ITRS99 model is that ways will be found to produce highly doped junctions with low enough resistivity to reduce junction sheet resistance at the same time as reducing junction depth. The target resistivities (see Fig. 1) are well below the "activation wall" at ~10^-3Omega-cm that characterizes results with present-day best methods, i.e., sub-keV boron implantation and "spike"-ramp rapid thermal annealing [3]. In contrast, the most aggressive dopant activation expectations in the ITRS99 study (sheet resistance of 100W/square and a junction depth of 8nm for 22nm gates) approach the resistivity of metal silicides, at about 10^-4Omega-cm.

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Junction abruptness. Controlling the total source-to-drain series resistance for sub-100nm transistors requires special attention to the contact resistance and the spreading resistance at the junction of the source extension and the channel [4, 5]. The key issue is the abruptness of the doping profile at the lateral edge of the source extension and its effect on the spreading resistance component of the total transistor series resistance. The ITRS99 study calls for lateral doping profiles that decrease into the channel region at a slope of ~3nm/decade in concentration for 100nm gates. Obtaining a lateral doping profile abruptness of <3nm/decade presents severe challenges for bulk silicon doping by implantation and rapid thermal annealing. As-implanted profiles for 0.2keV boron into pre-amorphized silicon have a vertical profile steepness of 2.5nm/decade [6]. The key S/D extension profile, in the lateral direction, still remains to be characterized and will be further broadened by thermal annealing in actual transistors.

SOI devices: A path to 25nm gates with 5-10nm thick channels

The best response to these challenges for transistor formation on bulk silicon is still an area of strong debate. Obtaining low contact resistance and abrupt junctions may have more leverage for net chip performance than S/D extension sheet resistance, for example [7].

Figure 3. Sketch of CMOS transistors for partially-depleted, fully-depleted, and thin-body SOI devices. The fully-depleted and thin-body SOI transistors are shown with dual gates.Click here to enlarge image

Another path is to explore the implementation of SOI wafer technologies, which offer new options for transistor design and ways to avoid many of the constraints for bulk silicon CMOS. With the 20-50% increase in transistor speed that can be achieved by switching to SOI [8, 9], the performance of ICs can be increased by the equivalent of one or two generations of bulk Si scaling without the cost of a shift to higher resolution lithography. SOI "dual-gate" and "thin-body" CMOS transistors provide excellent control for the off-current (leakage) characteristics that limit the endurance of battery-operated computer and communication devices. In addition, the soft-error immunity and radiation hardness [10] of SOI devices is seen as a key requirement for expansion of high data rate network servers that form the core of internet and other global data transfer links.

SOI-MOS devices with thin-body channels in the range of 1-5nm have been studied and show "well-behaved" characteristics [11-13]. In terms of the scaling trends from ITRS, a channel and extension thicknesses of ~5nm would be consistent with a gate size of ~10nm, which is five times smaller than the perceived "end of the roadmap" for CMOS transistors built on bulk silicon wafers.

Types of SOI materials and transistors

SOI materials are now being used with a wide range of Si-SOI and buried oxide thickness [14]. (See Fig. 2.) The applications for "thick" (>1mm) SOI include power IC switches, RF bipolar signal processors, and a wide variety of MEMS and optoelectronic devices. The principal SOI material at present for CMOS signal, logic, and memory applications is "thin" (50-1000nm) SOI.

Figure 4. Timeline of Si-SOI layer thickness linked to junction depth and gate size predictions from ITRS 99 [1].Click here to enlarge image

CMOS transistors in "thin" SOI are often "partially-depleted," i.e., the depletion depths of the fully powered CMOS channel are shallower than the thickness of the silicon layer. Under these conditions, switching speeds increase by 20-30% compared to equivalent circuits in bulk silicon powered at the same operating voltages [8, 15]. Alternatively, partially-depleted SOI devices can be operated at lower voltages and lower battery power drains with a significantly smaller speed penalty than bulk silicon devices. An immediately useful advantage of partially-depleted SOI is that circuit designs from bulk silicon devices can be imported into the SOI environment with only a modest investment in circuit redesign.

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For "fully-depleted" CMOS transistors, the Si-SOI thickness is the same as the channel and S/D extension depth. Although circuit designs need to take full account of the special conditions of operation in an SOI layer, the highest gains in circuit speed, reduced power requirements and highest level of soft-error immunity are realized with fully-depleted SOI devices. A sketch of these evolutionary types of SOI CMOS is shown in Fig. 3.

Comparison of ultrashallow junctions in bulk silicon and SOI

Recent advances in the quality and manufacturability of SOI materials have presented the IC industry with a serious new option to the device scaling scenarios that have been the basis of device and system advances for the last several decades. SOI wafers offer a means of increasing chip speed and decreasing power requirements without the cost and complexity of shrinking gate and junction dimensions. Secondary advantages, such as increased die count/wafer through reduction in the isolation area and improved resistance to soft-errors through the reduction in the volume of active silicon in contact with transistor and memory cell regions, will alter the dynamics of such diverse product segments as DSP, flash memory, and global enterprise database and network server nodes.

Figure 5. Nanocleave process flow for layer transfer production of SOI wafers.Click here to enlarge image

By relaxing the thermal budget constraints on dopant diffusion and activation, which limit bulk silicon processing, SOI devices offer the possibility of new paths to ultra-scaled devices. While the TCAD models for dopant distributions in thin-SOI CMOS need to be updated [16], the thermal budget constraints on vertical junction depth are essentially removed for fully-depleted CMOS devices. In addition, SOI technologies can be developed to include new device structures, such as dual-gate and high-mobility channel (with SiGe alloy layers) CMOS, that provide new tools for transistor designers to increase signal speed while decreasing off-current leakage levels. The transistor characteristics and process tradeoffs for bulk silicon and SOI wafers are summarized in Table 2.

Figure 6. Plasma immersion ion implantation (PIII) a) concept and b) SiGen PIII system with automated cassette-to-cassette processing.Click here to enlarge image

The timeline for Si-SOI thickness can be linked to the ITRS99 projections for bulk silicon CMOS by linking the silicon thickness to approximate design rules of T_Si approximately equal to 2 x X_j(S/D contact) for partially-depleted CMOS, and T_Si approximately equal to X_j(S/D extension) for fully-depleted CMOS, as shown in Fig. 4. For gate sizes of 140nm down to 70nm (up to about 2005), Si-SOI layer thickness is expected to be a mix of partially-depleted CMOS for mainstream logic and ASIC devices, and some fully-depleted SOI for high-performance processor and server
outer devices. For CMOS gates in the scale of 50nm, beginning in 2005-06, the multitude of process and performance issues described in the ITRS99 study will preclude the use of planar CMOS on bulk silicon as well as in partially-depleted SOI. By migrating mainstream transistor architectures to fully-depleted SOI, CMOS circuit methods could be extended a full decade beyond the "end of roadmap" for planar CMOS on bulk silicon. Thin-body SOI, with gate sizes at 20nm on Si-SOI layers of ~10nm, are now the threshold of research devices [11-13]. If device scaling continues at the historical rate of a 0.7 shrink every three years, these devices would be in production at about 2015.

Atomic layer cleaving for SOI wafers

Figure 7. SEM images of the SOI layer edge profile for a) as-cleaved and b) fully-processed Nanocleave SOI wafers.Click here to enlarge image

The key to the use of SOI wafers for fully-depleted CMOS is control of the thickness of the Si-SOI layer to within a few percent. This level of thickness control becomes increasing difficult for fabrication methods that require extensive chemical etching, CMP or similar mechanical polishing methods to obtain sub-100nm Si-SOI layers and to remove damage layers. An atomic layer cleaving process has been developed for layer transfer (or "bonded") SOI with an as-cleaved local surface roughness of less than the lattice constant of silicon (5.43Å).

This SOI fabrication process, Nanocleave, begins with the formation of a cleave plane, an oxide layer, and an Si-device layer on a "donor" wafer (Fig. 5). A bonded wafer pair is then created with the donor and an oxidized "handle" or device wafer. Since the bond strength of the donor-handle interface is significantly higher than the interface strength at the cleave plane, a novel cutting process is used to separate the Si device layer from the donor wafer, creating an SOI structure on the handle wafer. In the Nanocleave process, the donor wafer cleaving is done at room temperature using the drive force of a static pressure of N₂ gas to cleave and separate the wafers. The result is an SOI wafer with a routine control of Si-SOI thickness within ±1% over a 200mm wafer.

Production tools for ultrathin SOI

Development of automated process tools for cost-efficient, high-volume production of SOI wafers is as important as the fundamental process itself. In addition to the standard Si front-end process tools used for most of the Nanocleave process steps such as thermal oxidation furnaces and automated wet-etch benches, automated tools have been developed for the critical steps of plasma activation, bonding, and room temperature cleaving.

Plasma immersion ion implantation

The implantation step in the Nanocleave process is designed to obtain optimal cleaving action at room temperature. For thin-SOI, with Si layers in the range of 50-400nm, a standard high-current ion implanter can be adapted to produce modest volumes (5-20k wafers/month) of 200mm SOI wafers. For Si device layers thinner than 50nm, the range of the ions used in this process dictate that efficient techniques must be available to implant these ions at low energies. Since these ion energies are approaching the low end of the capabilities of beamline ion implantation systems, plasma immersion ion implantation (PIII) has been industrialized for SOI production [17]. In PIII processing, the wafer is in direct contact with the ion source plasma (Fig. 6) without the mass selection and beam transport regions that are present in beamline ion implantation.

With the PIII approach, high flux ion implantation is possible at all energies that can be supported by the power supply and system scale, which is particularly advantageous for the implantation regime of high dose (>10¹⁵ions/cm²) at energies under 10-20keV. Another advantage of PIII processing is that the implantation time (and hence the throughput for high dose implants) is independent of the wafer area, as long as the PIII system is scaled large enough to include the entire wafer along a plasma boundary. This means that the productivity advantages of PIII techniques increase as the wafer size grows.

Room temperature, atomic layer cleaving

When the cleave plane is defined with atomic layer precision with a sufficiently low cohesive energy, the propagation of the cleave front across the wafer can be controlled in a highly reproducible manner. A fully automated tool that separates bonded donor-handle pairs by cleaving with a static pressure of N₂ gas at room temperature is shown at the beginning of this article.

The atomic layer nature of the selection of the cleaving plane results in an as-cleaved surface finish of 4Å ±2Å (RMS, measured by AFM over a 10mm x 10mm region), which is routinely obtained. This degree of smoothness requires no CMP polishing. After final anneal and cleaning, the SOI wafer finish is in the range of 1-3Å.

In addition, the termination of the SOI layers along diagonal crystal planes results in smooth and regular edge profiles without the need for edge polishing. SEM images of the SOI layer edge profiles, as-cleaved and after final anneal and clean, are shown in Fig 7.

Conclusion

SOI wafers are opening a path for the extension of planar CMOS transistor design to perhaps a decade beyond the "end of roadmap" limits foreseen in the ITRS99 study for 50nm gates on bulk silicon. Operational SOI transistors have been studied with gate sizes as small as 25nm and Si channel thicknesses of 1nm. The migration of high-performance IC devices to SOI is already under way. Led by IBM [18], the improved performance of IC devices fabricated on SOI wafers for high switching speeds and low-power operation has been recognized as a significant advantage for CPU and microprocessor logic.

The key to this technology path is development of methods to fabricate thin-SOI wafers with high levels of control for silicon thickness, electrical properties, and interface characteristics. Extensions of atomic layer cleaving methods and tools, which provide 1% control on silicon layer thickness for 200nm SOI, to the "ultrathin" (10-50nm Si) and "nano" (5-10nm Si) SOI regimes offer promise to provide silicon materials of appropriate quality and at economically viable cost for CMOS circuit designs well into the second decade of the twenty-first century.

References

1. International Technology Roadmap for Semiconductors, 1999 Edition, Semiconductor Industry Association, San Jose, CA 95110.
2. "Proc. 5th Inter. Workshop on Measurement, Characterization and Modeling of ultrashallow Doping Profiles in Semiconductors," J. Vac. Sci Technol. B18, pp. 337-604, 2000.
3. A. Agarwal, A.T. Fiory, H.-J. L. Gossmann, C.S. Rafferty, P. Frisella, "ultrashallow Junction Formation by Spike Annealing in a Lamp-Based or Hot-Walled Rapid Thermal Annealing System: Effect of Ramp-Up Rate," Materials Sci. in Semiconductor Processing 1, pp. 237-241, 1998.
4. C.M. Osburn, I. De, K.F. Yee, A. Srivastava, "Design and Integration Considerations of End-of-the-Roadmap ultrashallow Junctions," J. Vac. Sci Technol. B18, pp. 338-345, 2000.
5. K.K. Ng, W.T. Lynch, "The Impact of Intrinsic Series Resistance on MOSFET Scaling," IEEE Trans. Electron Devices, ED-34, pp. 503-511, 1987.
6. M.I. Current, et al., "Process Integration Issues for Doping of ultrashallow Junctions," J. Vac. Sci Technol. B18, pp. 468-471, 2000.
7. P. Keys, H.-J. Gossmann, K.K. Ng, C.S. Rafferty, "Series Resistance Limits for 0.05mm MOSFETs," Superlattices and Microstructures, Vol. 27, pp. 125-133, 2000.
8. G. Shahidi, et al., "Mainstreaming of the SOI Technology," Proc. IEEE Inter. SOI Conf., pp. 1-4, 1999.
9. E. Leobandung, et al., T.-C. Chen, B. Davari, G. Shahidi, "High Performance 0.18mm SOI CMOS Technology," IEDM-99, pp. 679-682, 1999.
10. S.T. Liu, W.C. Jenkins, H.L. Hughes, "Radiation Response of SOI Materials," Electrochemical Soc. Proc. 99-3, pp. 225-230, 1999.
11. H.-S. P. Wong, D.J. Frank, P.M. Solomon, "Device Design Considerations for Double-Gate, Ground-Plane and Single-Gated ultrathin SOI MOSFETs at the 25nm Channel Length Generation," IEDM-98, pp. 407-410, 1998.
12. Y.-K. Choi, et al., "Ultrathin Body SOI MOSFET for Deep Sub-Tenth Micron Era," IEDM-99, Paper 3.7, 1999.
13. T. Ernst, et al., "Ultimately Thin SOI MOSFETs: Special Characteristics and Mechanisms," Proc. IEEE Inter. SOI Conf., pp. 92-93, 1999.
14. J.P. Colinge, Silicon-on-Insulator Technology, 2nd ed., Kluwer, 1997.
15. White paper on SOI at www.chips.ibm.com/bluelogic.
16. H. Park, et al., "Dopant Redistributions in SOI During RTA: A Study on Doping in Scaled-Down Si Layers," IEDM-99, pp. 337-340, 1999.
17. M.I. Current, et al., "A Plasma Immersion Implantation System for Materials Modification," presented at Plasma-Based Ion Implantation 1999, Nara, Japan, to appear in Surfaces and Coatings Technology, Elsevier.
18. P. Smeys, et al., "A High Performance 0.13mm SOI CMOS Technology with Cu Interconnects and low-k BEOL Dielectric," IEEE Symposium on VLSI Technology, pp. 184-185, 2000.

Michael I. Current is the director of technology marketing at Silicon Genesis, and has worked at Applied Materials, Kyoto University, Xerox/Palo Alto Research Center, Trilogy Systems, Signetics, Cornell University, and Rensselaer Polytechnic Institute. He received his PhD in solid state physics from RPI and is an active member of the MRS, AVS, and Bohmishe Physical Society. He was the founding president of the Greater Silicon Valley (Ion) Implant Users Group. Silicon Genesis Corp., 590 Division St., Campbell, CA 95008; ph 408/871-3082, fax 408/871-8607, e-mail [email protected].

Stephen Bedell is the manager of strategic technology at Silicon Genesis. He received his PhD in physics from the State University of New York at Albany. He has worked with Sematech, Semiconductor Research Corporation, and Rensselaer Polytechnic Institute. Bedell is a member of Sigma Pi Sigma, MRS, and AIP.

Igor J. Malik is the director of product development at Silicon Genesis. He holds a PhD in chemistry from the University of Illinois at Chicago, and he has worked at Chartered Semiconductor/Institute of Microelectronics, OnTrak Systems, and MEMC Electronic Materials.

Lucia M. Feng is a senior program manager at Silicon Genesis. She received her PhD in materials science and engineering from the University of California, Berkeley. Feng has worked at Applied Materials and has been the chair of the Plasma Etch Users Group of the Northern California Chapter of American Vacuum Society since 1998.

Francois J. Henley is the president, CEO, and a founder of Silicon Genesis. He was also the founder, president, and COO of Photon Dynamics, and the founder and principal engineer at Dataprobe Corp. Henley holds a BSEE degree from Rensselaer Polytechnic Institute and an MSEE from the University of California Berkeley.