A closer look at some of the most difficult processing challenges
09/01/2000
Pieter Burggraaf, Senior Technical Editor, Solid State Technology
overview
From the "red brick wall" of processing uncertainties as we strive to remain on the track of Moore's Law, some of the trickiest and most uncertain challenges are emerging. Consider, for example: the current and forecast state of optical lithography; two- and three-dimensional dopant profile spatial resolution needs; detecting defects associated with high-aspect-ratio structures; the reduction of water and chemicals use; and reducing the time from fab groundbreaking to first full loop wafers out to <12 months by 2008. Here we will describe these challenges and some of the potential solutions being explored.
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There is no shortage of difficult processing problems facing semiconductor fabs if they are to achieve the progress being projected for the next few years. The 1999 International Technology Roadmap for Semiconductors (ITRS) named a host of them: in fact, each chapter begins with a list of five or more.
A core technology with many uncertainties is lithography, often called the wheel with which chipmakers spin their gold. The ITRS calls it "the key enabler and driver for the semiconductor industry."
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A curious thing happened on the way to 2000: The gloom and doom over the death of deep-UV (DUV) optical lithography capability and the incredibly steep learning curve involved with contending next generation lithography (NGL) choices turned out to be overblown, or at the least, premature. As the industry booms, it turns out that the state of optical lithography appears to be promising on all three exposure wavefronts: 248nm, 193nm, and 157nm (Fig. 1).
While 193nm scanners (some would argue 157nm) are the emerging lithography tools for features at or near the 100nm technology node, some surprising advances promise to push existing lithography further than expected. Recent state-of-the-art experiments by researchers at MIT Lincoln Labs, using reticle enhancement techniques and Numeritech software, have achieved sub-100nm lithography features with a rather ordinary 248nm DUV stepper [1]. The implications are enormous for semiconductor manufacturing. These techniques might be applied more quickly than new stepper/scanners will be available, and they do not involve costly development work and equipment and fab changes. But these results are for widely spaced CMOS transistors, and scaling to dense circuits continues to be very difficult.
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Figure 1. State-of-the-art optical lithography results showing a) 248nm lithography etched 50nm polysilicon gate features (the residue is due to an incomplete LOCOS strip process); b) nonoptimized 193nm lithography results on silicon using DUV 300 ARC yielding 75nm and 65nm line features in 2800Å Sumitomo 700 resist, and 130nm contacts in 2800Å Sumitomo 655 resist; and c) early work with 157nm lithography. (Sources: a) Fritze, MIT Lincoln Lab; b) International Sematech and SVGL; and c) Schurz, Ultratech Stepper)
"Also," notes Eric Johnson, VP of technology at Nikon Precision, "phase shift reticles eat up a much larger percentage of the imaging costs than lithographers are accustomed to."
So, continue with 193nm lithography
In late 1999, we were anxiously awaiting the first shipments of 193nm scanners and the emergence of resist samples. "Now," says Dan Williams, manager of technology and applications at FSI International's Microlithography Division, "all the pieces for 193 — scanners, resist, and clusters — are available and we're working toward actual production implementation."
 Figure 2. Correlation of in-line junction depth measurement, using carrier illumination, to drive current for 180nm NMOS transistors. (Source: Kluth, AMD, and Boxer Cross). |
Availability means low-volume shipments of ~0.60NA-class exposure tools; availability of next generation ~0.70NA-class tools (a.k.a: "production tools") is promised for early 2001. And 193nm lithography still needs an extremely low bandwidth 4kHz 20W ArF laser to make the cost of operation lower. "Available also means relatively immature 10nm/°C sensitive (with some single digit results) chemically amplified (CA) resists, still working toward the targeted 3nm/°C. But current 193nm resist is not unlike early resists for 248nm lithography, where the first releases came in around 16nm/°C. As for cluster processing capabilities, the demand is for tighter CA resist processing bake and time delay uniformities, better dispense and develop characteristics, and increased sensitivity to amines," says Williams.
 Figure 3. Multiperspective laser scanning. (Source: Applied Materials) |
Despite this progress, experts still argue over 193nm lithography's insertion point in wafer processing production. John Shamaly, president of SVGL, says, "We are confident that 193nm lithography will enter production at the 130nm node and these tools will drive it down to 100nm." In another camp, Chris Rowan, senior director of strategic marketing at Cymer Technology Inc., says, "While there are some powerhouses looking at 130nm with a backup plan in hand, we think the insertion point is being pushed out and see that the vast majority of users will first use 193nm at the 100nm node, late in 2002 or early 2003. This is because 248nm is being pushed and also because the 193nm infrastructure is not completed yet."
In reality, at the 130nm node, lithography is more a question of economics than technology. Johnson notes, "Some customers believe in pushing KrF by any means possible, including more expensive reticles. Others (such as foundries, which run many fewer wafers/mask on the average) prefer the 'simpler' approach of driving to a shorter wavelength."
Then, on to 157nm lithography?
Optical lithography's last hurrah (you've heard that before, but few discuss any merits to 126nm optical lithography) continues to swell on the momentum of periodic rallies of 157nm enthusiasts. These include worldwide tool and materials suppliers, chipmakers, consortia, laboratories, and academia. Their most recent meeting was the First International Symposium on 157nm Lithography in Dana Point, CA, in May. (The fact that this meeting was sponsored by 43 companies should say something about the 157nm wavelength.) The summary highlight of this meeting was "substantial progress especially in pellicle and resist developments."
Gene Feit, manager of resist development at International Sematech, says, "Three companies reported establishing platform feasibility. This is the first evidence that we can overcome the high absorbance at 157nm of most organic materials and existing resists."
For pellicles, three other companies presented results showing progress with polymer material and so-called hard pellicles. The polymer materials are now being evaluated for transmissivity and durability at MIT Lincoln Laboratory.
Somewhat like 193nm, timing for 157nm is a critical issue. Gerhard Gross, director of lithography at International Sematech, says, "If we cannot have tools ready by 2003, it will be too late to use 157nm technology."
Resist development microstepper exposure tools have been in place for about a year. Solid State Technology's staff has seen a miniscanner at SVGL, now fitted with optics, that will ship this year; the equivalent full field tool is still slated for 2001. Crucially important, scanner makers and their optics partners are cleverly building calcium fluoride (CaF2) supply or, equally cleverly, building optics designs around projections of CaF2 supply.
Rowan says, "We've run a [157nm] F2 laser at 2kHz so power should not be an issue for process development tools. But because the optics have lower transmittance than 193nm, higher power sources are required to enable high-throughput tools and reduced cost/layer. Extreme rep rate is going to be required and there are key bandwidth issues that have to be developed independently for catadioptric or refractive approaches."
Paul van Attekum, ASML VP of product marketing, states, "Whether 157nm equipment is in time depends on what you believe the node will be; 70nm puts the timing at 2003 with volume in 2005. Then, materials and tools will be ready." ASML has started a program to participate in the development of the 157nm tool it is building and in a "total process" oriented pilot activity driven by Belgium's IMEC to stimulate and support the build up of the complete infrastructure (tool, resist, reticles, tracks, etc.).
The nemesis of 157nm is 193nm progress and NGL options. "Once in place, don't be surprised by how far users will try to push 193nm lithography," says van Attekum. Johnson says, "There seems to be a general consensus that the 100nm node can be covered by ArF [193nm] which puts the 157nm insertion realistically at 70nm, at least for production, where some feel projection e-beam could be a credible option. It is possible that both technologies will be used depending on the application and the customer."
Profiling atoms
Metrology offers a wide range of potential problems, but measuring doping profiles will become prominent as devices shrink. Consider the need for 2- and 3-D dopant profile spatial resolution being driven down to 1.5nm (15Å!) for the 100nm technology node by 2005, part of the ITRS "emerging overall challenge of metrology tools to measure properties on atomic distances" and the interplay of statistical results.
Curiously, metrology for ion implant dopant profiling is an eclectic collection of the classic (e.g., SIMS) and established (e.g., thermally modulated optical reflection, which measures total dose). Emerging new technology adds capability to these widely used methods rather than supplanting them. One of the newest buzzwords in ion implant metrology is the application of carrier illumination, using an interference measurement (a <2µm spot on patterned wafers) of reflection off a quasi-static carrier distribution.
Alain C. Diebold, International Sematech senior fellow and manager of metrology, tells Solid State Technology, "Carrier illumination is the emerging new technology for ultra-shallow junction (USJ) depth metrology on both as-implanted annealed samples and nonimplanted doping (e.g., CVD layers). Since this technology is sensitive to active carrier concentration, it is capable of measuring junctions produced by nonimplant doping technology." AMD and Boxer Cross have shown that carrier illumination measurements can be correlated to drive current for 180nm CMOS transistor technology (Fig. 2).
Peter Borden, CTO at Boxer Cross, says, "Our field evaluations on both patterned and bare wafers demonstrated electrical correlation to transistor performance, test structure probe measurements, and physical correlation to existing junction characterization methods. We have determined that this method is suitable for both post-anneal junctions and measurement of the depth of amorphous layers used in pre-amorphization implants that often precede USJ implants. This enables statistical process control characterization of activated USJ layers (source-drain and extension) immediately after anneal."
Borden says, "For USJ implants the dose control problem today is really a combined implant-anneal issue, because of the rapid movement of dopants, especially boron, during anneal, and the low thermal budget that forces a tight balance between junction movement and complete dopant activation. This means that it will be important to characterize the junctions after the anneal. In addition, the process window will be very narrow because it is so difficult to get a shallow, low-resistance layer, especially with a very short spike anneal where the ramp up, ramp down, and peak temperatures [have] to be precisely controlled."
The statistical nature of ion implantation is a key limitation. David Hodul, application marketing manager at ThermaWave, says, "Consider that threshold adjustment implants will be in the hundreds of atoms/gate range at the 130nm-technology node. For a device with 10 million transistors, some gates will get 60 atoms and some 140 atoms." Measurements can be averaged over larger areas and measured for control purposes, but the spread in electric properties will be larger "for statistical reasons than for across-wafer or wafer-to-wafer spreads." Hodul says, "When the statistical spread in dose is much larger than average variability, a choice needs to be made between the cost of yield losses at sort and the cost of the metrology tool...You can't control the statistical variation. The roadmap also has requirements for measuring profiles to depth resolutions where similar statistical issues arise. A single dopant atom electrically affects hundreds of angstroms around the atom. In this case, it's not clear what depth resolution to tens of angstroms means physically."
One advantage here is that advanced ion implanters, with good dose control and in situ dose monitoring, require only occasional checks to make sure they are properly matched.
Deep defects
Particularly intriguing with dual-damascene, trench capacitors, and other processing advances is the challenge of detecting defects associated with high-aspect-ratio structures, especially defects near or at the bottom of these features. The ITRS defines this as depth-to-width ratios >3, footnoting the need to detect uninterrupted monolayers of material at the bottom of structures. The basic problems are poor transmission of energy used by conventional defect detection tools down into IC structures and back out, and the large number of these structures to inspect, particularly with dual damascene technology.
Interestingly, the required state of the art for straight defect detection (not the monolayer challenge) is continuing to emerge out of the extension of light scattering, optical imaging, and e-beam imaging technologies.
E-beam imaging, albeit low throughput, with improved voltage contrast has the ability to find defects in up to 14:1 aspect ratios.
It can even detect subsurface problems such as voiding in copper or open contacts.
One new twist to light scattering optical inspection technology is so-called multiperspective laser scanning, a technique that came out of work by Applied Materials for International Sematech's high-aspect-ratio inspection (HARI) project.
Ofer Milstein, director of marketing at Applied Materials' Process Diagnostics and Control Group, explains, "Our work on this project looked at a full range of wavelengths, and elevation and azimuth angles, along with numerical simulations, to learn how light can penetrate and return from contacts." The first commercial rendition of this development work combines six different perspectives and three kinds of information (i.e., four darkfields, one brightfield, and one "grayfield") analyzed together to provide the best possible separation of defect data from the background noise for a given application (Fig. 3).
 Figure 5. Photoresist strip rates with Semitool's HydrOzone process for various photoresists and processes (nonimplanted). |
Along with the combination of three perspectives, "grayfield" is new; it is described as an annular darkfield detector normal (i.e., 70-80°) to the wafer, and it is in addition to grazing angle detectors. "This covers many of the critical defect categories not previously detected by non-SEM technologies, even on the most critical gates and interconnect layers, or defects like bridging or 3-D defects...hidden between lines where it is very hard to see them with darkfield because the lines hide the bridging," says Milstein.
Extension of optical imaging to find high-aspect-ratio defects is coming in the form of shorter wavelengths. Tom Long, VP of corporate marketing at KLA-Tencor, says, "Solutions need to address high aspect ratios plus resolution of the critical defects for the design rule it is applied to; if you cannot resolve the defect, you cannot solve the problem." Thus, much like optical lithography, optical imaging for defect detection is being extended with brightfield optical inspection tools that incorporate 248-365nm UV wavelengths and high-numerical-aperture optics, combined with better system stability to improve focus and edge-contrast enhancement that rejects background noise. Performance with UV defect inspection is on the caliber of finding defects in 8:1 aspect ratios on sub-0.2mm structures.
Long says, "The combination of optical and e-beam is still critical in developing processes in yield learning phases, very critical in the pilot line transfer and the yield ramp of a fab. With the proper tools applied to the problems, they can be found."
It is, however, the quest for an effective solution to the detection of a very thin residue at the bottom of a single deep structure that demands fast development of novel methods such as holographic imaging, e-beam (scattering or imaging), acoustic techniques, or x-ray imaging. According to KLA-Tencor, e-beam inspection with its ability to find voltage contrast defects is also a technology being used to address this problem.
Saving water
While chip manufacturers often see themselves as leaders in environment, safety, and health (ESH) issues and, perhaps, participants in one of the planet's greenest industries, this industry's potential for ESH problems is watched closely. So it is no secret that ESH integration is every bit as crucial as process integration. The ITRS says, "...ESH must be integral to the thoughts and actions of process, equipment, and facilities engineers, and to university researchers ... [and] must meet local, national, and international needs, with positive impact on cost, technical performance, and product timing, and minmization of ... environmental impact."
From the list of difficult ESH challenges, the reduction of water and chemicals use is a critical one for chipmakers.
Increasingly, fabs are moving to or expanding in regions particularly sensitive to water supply (e.g., TSMC in Tainan, Taiwan, Intel in New Mexico and Arizona, etc.). Among the first issues raised in the media — often the first thing the public learns about an arriving semiconductor manufacturer — is that traditionally wafer processing uses strong liquid chemicals that necessitate large volumes of rinse water and associated disposal.
Solid State Technology calculates that the semiconductor industry used 225 billion liters of water in 1999 [1] (enough water for 326 million adults to drink the recommended eight glasses/day for one year). Without a major effort here, industry megatrends — specifically increases in wafer size, a growing need for higher water purity, and increasing numbers of process steps — inherently work against reductions in chemical and water use rates. But reduce it we must. Tagging current factory integration feed-water usage at 7.6 liters/cm2 of silicon, the ITRS calls for a 62% reduction by 2005 (to 2.9 liters/cm2) and an 84% reduction by 2014 (to 1.2 liters/cm2). The ITRS 62% reduction challenge has to occur during a period when silicon use will continue to grow at a compound annual growth rate of 10.3% [3], but the combined effects will reduce industry water use to ~154 billion gallons by 2005.
Perfect solutions
Interestingly, this is an area where there are a growing number of potential solutions. Jeff Butterbaugh, applications development manager at FSI Surface Conditioning, says, "The issue is more one of real-time adoption of some of the latest cleaning technologies. Fab engineering groups tend to focus on etch, lithography, and materials that are more directly related to devices. To them, cleaning chemistry is a safety net."
It is clear the driver that will achieve better resource conservation must be a top-down management directive that addresses environmental impact. Here, European companies have notably taken a lead (e.g., from http://eu.st.com consider the mantra "TQEM @ STMicroelectronics: The world is priceless; ecology is free). Unfortunately, the impetus to change with the adoption of 300mm wafers is less likely because of the industry's convention of making as few changes as possible at once.
Seemingly, the biggest gains will be made with the somewhat proven combinations of spray-application and ozone-based chemistries that already provide ITRS-caliber reductions in both chemical and water use (Fig. 4). While wet bench technology has a state of the art itself, including reduced bath volumes and cassetteless processing, spray tools inherently provide a significant savings in water and chemical use. In addition, ozonated cleaning chemistry, with the ability to blend chemicals at the point of use, has reached the maturity that the industry needs.
Craig Meuchel, process engineering manager for Semitool's surface prep division, says, "In the past the ozone-water process was too slow and it was unable to deal with the range of different cleaning combinations coming through a fab. Today, we are seeing process and device results comparable to or better than current Piranha processing" (Fig. 5).
Other advances come with wet-chemistry single wafer processing. Michael West, VP of strategic business development at SEZ Holding Ltd., says, "With single wafer based advances over traditional wet bench chemistry, in addition to the saving in chemicals and water, it is also important to consider the reductions in other consumables such as exhaust, electrical, and footprint, which can be... 50%." SEZ's DI water consumption is 1/10 (10%) or a 90% reduction when compared to a wet bench for the same application.
Along with these successes, there is an array of emerging alternatives to conventional wet cleaning technologies that hold promise. Among them:
- Ultra-dilute ammonia megasonics. This technology dissolves ammonia gas in DI water (~100ppm) at the POU, as a replacement for SC1-clean chemistry and particle removal (i.e., FSI's Yield Up Engineering).
- Anhydrous HF vapor for native oxide removal. This technology is being developed to include UV chlorine photochemistry and can be integrated as a dry clean technology on single wafer tools (i.e., FSI's Excaliber).
- Cryogenic aerosol technology, where cooled argon and nitrogen are partially liquified then injected into a vacuum chamber to form ice crystals that scrub the wafer. This has no chemical or DI water consumption at all and is particularly useful for BEOL processes.
- Super critical CO2 cleaning, developed at Los Alamos National Labs. In the supercritical state — 31°C and 1070psi — CO2 becomes a supersolvent. This property can be enhanced by the addition of a wide variety of dissolvable co-solvents, usually soluble in the range of 1-5%. This process is being developed for photoresist strip as a single wafer, all dry process that uses no DI water (i.e., SC Fluids Inc., a division of GTI).
Factory operation and integration
The ITRS states, "The current industry transition to 300mm wafers is seen as the most significant opportunity in the history of the semiconductor industry to collectively and systematically control and lower manufacturing costs." Buried within all the challenges associated with bringing 300mm fabs online is an interesting industry roadmap line item: reducing the time from groundbreaking to first full loop wafers out from <18 months to <12 months by 2008.
Amazingly that would be getting to the grand opening of a super wafer fab in nearly the same time as a Super-Walmart. Mihir Parikh, CEO at Asyst Technologies, says, "Much like the auto industry, our industry has to be able to do this in terms of process generation changes." At first blush, this challenge seems like it just involves construction issues, but deep down it doesn't. It is also significant that a "copy exact" philosophy will not necessarily work because, increasingly, new fabs are not built to support large volumes of the same IC product.
Most of the key elements to meet this challenge were addressed by Intel's Mike Splinter, speaking last year to the equipment community. "The lead time for equipment needs to be cut in half; six months to a year for a piece of equipment is too long, and it also contributes to volatile industry cycles. If lead times were shorter, equipment orders could be based on predictions that are more likely to still be valid when the equipment arrives." Splinter also stated that equipment must reach full functionality more quickly to keep factory costs down. Here, help is expected through "e-diagnostics" — monitoring equipment via the Internet." Parikh says, "More than just [having] process capability, equipment has to be hardware and software connectable to a factory the minute it is rolled in."
Dave Joseph, VP of products and methods at PDF Solutions, says, "Beyond operational issues, design-process integration (bringing the process and product together early), and...addressing systematic yield losses (as opposed to random yield losses), is a key to future fab ramps that are becoming more extreme as the industry moves more to consumer-based product lifecycles."
Briefly described, PDF Solutions works with historical design and fab data to build a set of characterization vehicles, replacing the historical SRAM test structure, targeting module-level (metal, via, contact, and poly), integration-level (FEOL and BEOL), and circuit-level (figure of merit circuits, IP cores, I/Os, PLLs, etc.) models used in their raw form to characterize process capability, and are fed to software modeling tools to understand yield and performance impact.
"From our view the biggest [thing that keeps] you from ramping quickly is inadequate integration as reflected by the product needs within the process," says Joseph.
How about you?
This short list of major challenges by no means contains the only tricky problems that must be addressed if the industry is to maintain its momentum. If you have some particular concerns you would like to see addressed, please e-mail me at [email protected].
References
- M. Fritze, et al., "Chromeless phase-shift masks used for sub-100nm SOI CMOS transistors," Solid State Technology, July 2000, pp. 116-131.
- 29.7 billion cm2 of Si used in 1999 (Dataquest) x 7.6 liters of feed water/cm2 (ITRS 1999).
- Dataquest Semicon West Forum, July 12, 2000.