Direct temperature metrology helps minimize CA-resist CD variation
09/01/2000
Jeffrey M. Parker, SensArray Corp., Santa Clara, California
Kim R. Dean, Daniel A. Miller, International Sematech, Austin, Texas
overview
PEB temperature is critical during the processing of chemically amplified 248nm (and below) photoresists. Variations in temperature directly affect CDs of final resist patterns. Many other process parameters can also influence CDs, however. Work with an instrumented wafer for direct, precise temperature measurement and mapping of wafer temperature over time during a PEB cycle has helped separate out CD variations caused by PEB temperature from those due to other factors. This has allowed improvement in the control of PEB hotplate temperature, virtually eliminating PEB temperature variation as a significant cause of CD variability.
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The skills of a detective (a lithography development engineer) are often required to isolate the source of contributors to critical dimension (CD) variation so that they can be controlled. What makes this work so daunting is that CD variations can creep in almost anywhere. Possible causes include mask variations, stepper errors in exposure or focus, delay between exposure and post-exposure bake (PEB), and a temperature deviation from setpoint or temperature non-uniformity across a wafer during PEB.
In addition to controlling traditional exposure performance metrics, such as depth of focus and exposure energy latitude, process engineers must now understand and control temperature variations that occur when processing thermally sensitive photoresists that help extend the capabilities of optical lithography.
Chemically amplified resist processing
Today's lithography is required to define <250nm features using chemically amplified (CA) photoresists. These are formulated to improve UV transparency (and sensitivity) at deep-UV exposure wavelengths of 248nm, 193nm, and 157nm [1]. Thermal processing is integral to the function of these resists: They rely on a heating cycle after exposure to activate, and a subsequent chill step to quench, a chemical reaction that enhances exposure sensitivity. The thermal sensitivity of the resist and temperature variation during this bake step directly affects dimensions of the exposed pattern.
During CA resist processing, wafers are baked immediately after resist application (post-apply bake or PAB) and again after exposure (PEB). The PEB is more critical because it activates the chemical reactions that catalyze the amplification of the initial UV-light-induced latent image. Within-wafer or between-wafer temperature variations during PEB (and also sometimes during PAB for resists having a lower activation energy) will contribute significantly to linewidth variation.
CA resists currently being used and under development differ widely in thermal sensitivity (Table 1).
Resist PEB sensitivity
The magnitude of CD change with PEB temperature must be known to discriminate between thermal effects and all other process variables. Figure 1 shows CD measurements vs. the PEB temperature setpoint for IBM Version 1B 193nm-resist [2-4]. These data, which were measured under constant conditions of resist thickness, soft bake time and temperature, and exposure settings, show that the average CD is reduced by ~4nm/°C increase in the PEB setpoint.
The CD budget
PEB temperature variations of a few tenths of a degree can use up a major portion and, in some cases, all of the allowable CD process variation "budget." Suppose, for example, 250nm-wide features must be printed within a tolerance of 10% (3s) using APEX-E resist. If the PEB hotplate has a 1°C variation, more than half of the CD budget or 16nm would be consumed (assuming 16nm/°C sensitivity, see Table 1). This leaves only 9nm in the CD budget for all the other process variables combined, including resist thickness, wafer flatness, focus stability, and develop uniformity. Clearly, the PEB deviation from setpoint and temperature non-uniformity must be controlled if CD variability is to be reduced.
One could choose a resist that has low temperature sensitivity, but there are tradeoffs that must be made. For example, although APEX-E has high-temperature sensitivity [5], it has found widespread use because of its excellent resolution [6].
In general, less temperature-sensitive resists have low activation energies (i.e., their acid-catalyzed deprotection reactions occurs at room temperature) and, as a result, these formulations sometimes have a limited shelf life [7].
Thermal metrology
Because variation in the PEB temperature of CA resists potentially can consume a significant portion of the CD budget, for effective process control it is crucial to have a means to conveniently and accurately monitor PEB temperature. In addition, thermal variation during resist processing is only one of many sources that contribute to the total CD variation, and it is important to be able to separate the causes of variation during process optimization and troubleshooting.
Test wafers and instrumented wafers are two methods that can be used for in situ thermal metrology: The test wafer technique is an indirect (temperature measurement) method because it involves coating, exposure, and development of a wafer with subsequent measurement of the resulting CDs. The variation in CD is used to infer some average variation in PEB temperature (or thermal dose) based on the known or previously measured sensitivity of the resist. The instrumented wafer method is direct because it uses thermal sensors embedded in the wafer to measure the actual temperature and temperature excursions in real time during PEB.
Investigating CD non-uniformity
Consider this example that illustrates how the root cause of a CD variation can be pinpointed using the traditional test wafer approach: CD-SEM measurements made to generate the resist sensitivity data of Fig. 1 showed that there was a large CD variation across the wafer. First, to determine if the PEB hot plate was the source of the variation, we placed exposed wafers at various rotational orientations on the PEB hot plate of an FSI Polaris 2000 microlithography cluster tool. We found that the CD variation was the same on all wafers, regardless of orientation. Thus, we concluded that the hot plate was not the culprit, but this work took ~12 hr.
 Figure 2. Contour plot of CD non-uniformity due to stepper exposure variation. |
Next, we troubleshot the stepper. We processed two sets of test wafers, rotating one set 180° from the other, in an Ultratech ArF microstepper. Subsequently we observed that the two orientations produced a reversal of CD variation between the two test wafer orientations, thus indicating that the stepper itself was introducing a CD non-uniformity of 70-80nm in a wedge-shaped pattern (Fig. 2).
While we were eventually able to find the cause of CD variation, directly measured wafer temperature on the hotplate using an instrumented wafer would have immediately eliminated the hotplate as the source of CD variation and saved considerable time.
Hotplate matching
To validate the speed and accuracy of the instrumented wafer technique, we compared this method to the traditional test wafer method to match and qualify hotplates. Just matching the hotplate setpoints is not good enough; the hotplate setpoint is not a reliable indicator of actual wafer temperature. In most CA-resist lithography processes, wafers are not in direct contact with the hotplate, but are heated in so-called proximity mode, where there is ~100mm film of air between the wafer and the plate.
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With proximity mode PEBs, the wafer and hotplate temperatures will differ.
This is because of heat loss from the upper wafer surface, exposure of the wafer to other factors influencing temperature (exhaust flow, purge gas flow rate, etc.), and the limited conductive heat transfer from the hotplate to the wafer. As a result, the setpoint temperature for different hotplates can vary substantially for the same effective wafer temperature.
Using CD measurements from coated, exposed, and developed wafers, we inferred the wafer temperature using the known CD vs. PEB temperature relationship. We used this procedure to match three hotplates on an FSI Polaris 2000 to within ±0.5°C. We coated and exposed APEX-E CA resist on 45 wafers using an Ultratech XLS DUV stepper. The PEB was done at 100°C in batches of 15 wafers/hotplate. We measured the CDs and correlated these measurements to plate temperature.
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When the mean temperature of a hotplate differed from the other hotplates by more than the specified tolerance, we adjusted the hotplate temperature, changing the setpoint offset, and repeated the process. This sequence of steps was repeated many times, until all three hotplates were matched to each other within the specified tolerance. Using this "trial-and-error" approach with test wafers, it took us ~2 weeks to match the three hotplates. (The 3s CD variation measured on the test wafers for the three hotplates are listed Table 2.)
After we matched hotplate temperatures using test wafers, we used a SensArray Process Probe RTD instrumented wafer to make direct in situ temperature measurements [8]. This wafer has an array of 17 resistance temperature detectors (RTDs) with an absolute accuracy of ±0.1°C and point-to-point profile precision of ±0.05°C. The instrumented wafer is used in conjunction with SensArray ThermalMAP temperature analysis software to view the entire thermal process cycle. The software maps wafer temperature in two dimensions and displays the result as a "movie" of temperature distribution changes over time.
We used the instrumented wafer system to characterize the same three hotplates that were previously matched using the test-wafer procedure. The test-wafer matching was done at 100°C.
We measured the hotplates at 120°C with the instrumented wafer. The previously measured 3s variation in CD was used to calculate a predicted PEB temperature range based on the known APEX resist sensitivity. These data, along with the actual PEB temperature ranges as measured by the instrumented wafer system, are tabulated in Table 2.
The temperature ranges (i.e., across-wafer variations) determined by the instrumented wafer are smaller than those calculated from the CD variation. One reason is the difference between the instrumented-wafer metrology and the test-wafer method. The instrumented-wafer temperature ranges were measured during steady state, after the wafer reached the nominal bake temperature of 120°C. The test-wafer CD variation is actually a measure of the time-temperature integrated thermal dose during a PEB bake at 100°C. In addition, the 3s CD data represent the total of all the sources of CD variation, not just the steady-state wafer temperature. By measuring wafer temperature directly, the influences of other bake parameters, such as exhaust flow, purge gas flow rate, and chamber design can be isolated from temperature and evaluated.
In a separate test, we used the instrumented wafer system to quickly match three new hotplates to the three existing hotplates on the FSI Polaris 2000. This procedure is normally a time-consuming task using test wafers and taking ~2 weeks vs. ~2 days using the instrumented wafers and analysis system. The results for matching to 94°C are shown in Fig. 3; Table 3 tabulates data for all six matched plates. The total temperature range for the three hotplates after matching was 0.51°C, compared to 1.17°C before matching.
CA-resist characterization
The magnitude of CD shift is a function of both temperature variation and bake time. The underlying steady state and transient components of the temperature profile are highly variable and are significant in analyzing PEB-induced CD shift [9]. These effects require process development engineers to investigate a variety of PEB time and temperature scenarios to find the optimum PEB recipe.
The real-time thermal profile data provided by in situ thermal metrology with an instrumented wafer can be used to study the behavior of new resists to pick the best PEB bake recipe. Running a set of tests at a series of setpoints and bake times can identify the CD changes due to transient and steady state components of the temperature profiles. For example, suppose a resist manufacturer suggests a range of PEB bake parameters of 90-100°C for 60-90 sec. A process engineer could run test wafers over a range of setpoints (e.g., every 2°C over 90-100°C) for various bake times at each setpoint (e.g., at 10 sec intervals from 60-90 sec.). The resulting CDs can be measured using CD SEM metrology and correlated with actual wafer temperature as measured by an instrumented wafer for the same PEB process recipe.
Direct temperature measurement
An instrumented test wafer with embedded sensors can measure both wafer temperature and wafer temperature history in situ on both hot and chill plates. This information can be displayed as a map that shows temperature variation across the wafer at each point in time. These data can be used to identify and correct across-wafer CD variation due to non-uniform baking for whatever reason. Armed with the capability of mapping temperature across the plate, one can select the most uniform hotplates for the most critical process steps and troubleshoot and correct other conditions, such as purge flow anomalies, that cause wafer-temperature non-uniformity during bake steps.
Using test wafers for in situ metrology has several limitations and is costly in terms of the wafers, resist, and stepper and SEM time consumed. A variety of factors, such as stepper exposure, must be held constant to isolate temperature effects. This further complicates an already tedious procedure. Since temperature may be deliberately or inadvertently varied during the process cycle, it is usually not possible to determine the actual thermal cycle history using test wafers.
Conclusion
Direct temperature measurement using instrumented wafers proved to be quicker and less costly than the conventional test wafer approach. The instrumented wafer approach takes ~2 days vs. ~2 weeks using test wafers. Direct measurement is also a fast way to uncover air-flow anomalies during PEB, detect and compensate for setpoint discrepancies, and uncover temperature non-uniformity problems that add to CD variation.
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Correlating in situ, real-time temperature data with actual CD data is a powerful analytical method for evaluating settings for the optimal bake cycle. The challenge for process developers analyzing the impact of different PEB temperature profiles is to isolate the temperature-specific influences on CDs, while keeping other CD influences constant. This method helps developers compensate for the dynamics of CA resists, however, and forms the basis for choosing an optimal setpoint and bake time. In situ thermal metrology also establishes a calibration database for the process conditions that were selected to guide installation and maintenance to ensure thermal uniformity.
Process researchers can use the real-time thermal profile data provided by in situ thermal metrology to study the behavior of new resists. By running a series of test wafers under different processing conditions and correlating the measured CD shifts with the temperature data, process developers can determine the best bake temperature setpoints and time at temperature during PEB. Once the relationship between temperature for a given CA resist and CD variation is known, tightly controlling temperature during thermal cycles provides a wider process margin during lithography thermal cycles to ease requirements for the more difficult-to-control process parameters.
The conventional test-wafer approach, which infers wafer temperature based on a process result, is limited in its ability to provide real-time data and results in a high cost in downtime. Direct in situ wafer-temperature measurement is a faster and more accurate approach to thermal metrology. It helps achieve tighter temperature control to virtually eliminate the influence of PEB temperature variation on CD variability.
Acknowledgments
We thank Danny Miller for sharing CD sensitivity data and James Beach for sharing data taken with the instrumented wafer system; both are at International Sematech. We also thank John Petersen of Petersen Advanced Lithography for helpful discussions.
APEX is a registered trademark of Shipley Company. ARCH is a registered trademark of Arch Chemicals. Polaris is a registered trademark of FSI International. Process Probe and ThermalMAP are registered trademarks of SensArray Corp.
References
- D. Seeger, "Chemically Amplified Resists for Advanced Lithography: Road to Success or Detour?" Solid State Technology, June 1997, pp. 115-121.
- K.G. Kemp, et al., "Effects of DUV Resist Sensitivities on Lithographic Process Window," SPIE Proceedings 1295, pp. 955-962, 1997.
- CD measurements were made at Sematech from cross-sectioned 250nm-wide dense features. PEB temperatures were varied ±5°C about the nominal bake temperature. IBM Version 1B resist was exposed at 193nm and 180nm-wide dense features were measured.
- R.R. Kunz, et al., "Advances in Resist Technology and Processing," SPIE Proceedings 1925, pp. 167-175, 1993.
- K.R. Dean, et al., "Airborne Contamination of DUV Photoresists: Determining the New Limits of Processing Capability," Olin Interface Proceedings 1996, p. 109.
- G. Amblard, et al., "Optimization of a Positive Tone Deep UV Process for Industrial 0.35µm Technology Production", Olin Interface Proceedings 1996, as quoted in G. Pawlowski, as quoted in G. Pawlowski, "Acetal-Based DUV Photoresists for Sub-Quarter Micron Lithography," Semiconductor Fabtech 6 1997, pp. 215-222.
- H. Ito, "Chemical Amplification Resists: History and Development Within IBM," IBM Journal of Research and Development 41, pp. 69-80, 1997.
- J. Parker, W. Renken "Temperature Metrology for CD Control in DUV Lithography," Semiconductor International, pp. 111-116, Sept. 1997.
- J. Lewellen, et al., "Effect of PEB Temperature Profile on CD for DUV Resists," SPIE Proceedings 3882, pp. 50-54, 1999.
Jeffrey M. Parker has a BA in computer science from UT Austin. He is a systems engineering consultant for SensArray Corp., 6448 Highway 290 East, Suite E-104, Austin, TX 78723; ph 512/450-1445, fax 512/374-1106, e-mail [email protected].
Kim Dean received her PhD from the University of Texas at Austin. Dean is project manager for 157nm photoresist development at International Sematech, Inc., 2706 Montopolis Dr., Austin, TX 78741; ph 512/356-3275, fax 512/356-5618, e-mail [email protected].
Daniel A. Miller is an engineering technician in the photoresist development group at International Sematech.