Adapting semiconductor processing tools to thin film head fabrication
09/01/2000
Thin films (GMR heads)
Paul Werbaneth, Sam Kirshman, Harry Slomowitz, Jim Thomas, Tegal Corp., Petaluma, California
overview
Thin film head manufacturers have leveraged equipment designed for IC fabrication, and this article reviews the impact on equipment design of the similarities and significant differences between the two types of products. A discussion of how various types of IC equipment were modified for the production of GMR thin film heads follows.
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Thin film head (TFH) fabrication is carried out in wafer fabs similar to those used for semiconductor device fabrication. The standard process flow of deposition, photolithography, and etch, along with electroplating and chemical mechanical planarization, is used to manufacture both advanced microprocessors and giant magnetoresistive (GMR) read/write heads. Semiconductor capital equipment vendors recognize that these commonalities lend themselves to adapting IC fabrication process tools to TFH applications, thereby gaining advantage by transferring existing designs and knowledge to a new market. Vendors who choose to go this route will find they need to surmount a significant early hurdle — the substrates used in TFH production are thicker, heavier, and more insulating (electrically and thermally) than any substrate encountered in semiconductor fabrication lines. Additionally, TFH substrates are typically square, and the industry has not standardized on substrate specifications. Every TFH maker may choose to employ a substrate unique to the company.
Manufacturers must address these known challenges, along with the inevitable unanticipated issues that will arise, in order to prepare any IC-ready thin film processing tool for TFH fabrication. Two areas in wafer processing tools that will require extensive modification to accommodate TFH substrates are general aspects of the wafer handling system and specific attributes of the process chamber. Based on our experience preparing a high-density plasma etch tool for TFH etch applications, we will comment here on wafer transport modifications, plasma reactor modifications, and some side issues (electrostatic discharge/ESD and corrosion control) important to economical processing of TFH wafers in production environments.
GMR thin film heads density trend
GMR read/write head fabrication processes for magnetic data storage are following the same kind of Moore's Law trend as that of semiconductors: annual performance enhancements (storage density here, measured in gigabits/in.2) are obtained by actively shrinking device features (the read stripe and the write pole for TFHs). The graphs presented in Figs. 1 and 2 illustrate these trends.
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A challenge for TFH fabrication is the continued problem of severe topography, even as read/write head feature sizes decrease [1]. IC makers have chosen to employ chemical mechanical planarization steps to eliminate surface topography in both front-end and back-end processes, realizing that deep submicron features are unobtainable without planarization. GMR head manufacturers are pursuing several alternative solutions to meet the challenge in feature size evolution, primarily higher-powered photolithography solutions and plasma etch.
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According to ASM Lithography, "The biggest challenge in this industry is to supply TFHs that satisfy the technical requirements at a competitive price. That is the reason the TFH industry is adopting many IC processes into their production, thus minimizing the development costs of the next-generation heads."
Several capital equipment vendors (Ultratech Stepper, ASML, SVGL, FSI) have announced deep UV photolithography solutions specifically geared toward advanced TFH processing, offering sub-0.25mm image resolution and the ability to handle round and square TFH substrates. This is a good example of extending proven TFH manufacturing techniques by applying technology already refined by IC manufacturers.
Plasma etching in GMR fabrication
Advanced TFH devices also require some new technology. Reactive plasma etch processes will be increasingly used in GMR head device fabrication as a means for the data storage industry to continue to support greater data density for magnetic disk drives. For example, fabrication of the top write pole in a read/write head for GMR devices is now an additive process, in which electroplated NiFe (Permalloy) forms the top pole structure. The shape and dimension of the top pole are established by a critical photolithography step prior to electroplating. The thickness of the imaging photoresist is often more than 5mm, and the top pole width is less than 1mm. The high aspect ratio makes it difficult to control the shape of the photoresist image, leading to varying dimensions of the plated top pole structure. These dimensional variations result in performance variations in finished read/write head devices, the magnitude of which may render the devices unusable.
Plasma etch processes can contribute to top pole fabrication for GMR devices in two ways. Photoresist descum, a plasma etch process, can improve the shape of the initial photolithography pattern, resulting in a tighter performance distribution across the tens of thousands of GMR read/write heads fabricated on a single wafer. A second way is using plasma etch processes to completely reverse the usual manufacturing flow: GMR head top pole fabrication becomes a subtractive process, in which the metal alloy is etched away except where it is covered by a photoresist mask. The advantages of plasma etch for GMR head top pole fabrication may include greater pattern transfer fidelity, allowing finer features with less CD variation. Plasma etch also allows the use of top pole alloy materials such as FeN, a sputter-deposited film that cannot be electrodeposited.
Figures 3 and 4 show examples of plasma descum and top pole etch. Many of the issues encountered in adapting plasma etch tools for TFH fabrication will be the same for any semiconductor capital equipment vendor contemplating this market. These issues begin with the TFH substrates themselves, and the differences introduced by them to established wafer handling and reaction chamber designs.
The TFH substrate
Table 1 is a summary of some of the important properties of silicon wafers and TFH substrates (also called wafers). While there can be common processes for ICs and TFHs, we can see that there are profound differences in the item being processed. Silicon wafers differ from TFH substrates in many significant ways — the TFH wafers are thick, high-mass, thermally and electrically insulating ceramic composites of which there is no standard type.
It is the last point, lack of standard wafer type, that remains vexing [2]. Table 2 shows various types of TFH wafers that could be used for advanced GMR device development. For silicon wafers for ICs, the only variables are the wafer diameter and configuration of the flat.
TFH wafer handling
Many thin film deposition, photoresist processing, and plasma etch tools are built around the cluster tool concept, in which a central wafer handling robot (located within a vacuum transport, or transporting wafers at atmosphere) moves wafers among stations arrayed around the central core. The processing stations could be photoresist spin modules, physical vapor deposition modules for seed layers, plasma reactors for either plasma-enhanced chemical vapor deposition (PECVD) of thin films, or plasma etch for thin film removal. Figure 5 shows an overhead view of a cluster tool platform used for plasma etch processing. As discussed in the following sections, modifications are required for each of the major cluster tool platform components.
Adapting wafer cassette platforms for TFH processing
Since TFH wafers come in a variety of shapes, sizes, and thicknesses, the cluster tool wafer cassette platform design will need to be adapted to accommodate these differences, along with the difference in the number of wafers present in a single cassette. The standard cassette for silicon wafer processing is designed to hold 25 wafers (13 or 25 wafers for 300mm wafers). The cassette design most commonly encountered in TFH processing holds 12 wafers. At the very least, the cassette platform control routines must learn not to expect more than 12 wafers, and they may also be required to modify platform motor vertical motion counts to account for the different wafer slot pitch in the 12-wafer cassette.
For the case of the many different TFH wafer sizes identified in Table 2, we employed a combination of off-the-shelf, modified off-the-shelf, and specially designed cassettes constructed from either metal or thermoplastic materials. These variations on the standard silicon wafer cassette also required us to modify our cassette platform design to improve the sensing of wafer cassette "present" and to rework the alignment blocks used for cassette positioning.
Adapting vacuum and atmospheric robots
The vacuum robot is the core robot in the center of the cluster tool. This robot moves wafers in a vacuum environment from the input cassette (located in the input cassette loadlock) to the aligner station. Wafers aligned for the process modules are then moved from the wafer aligner into either of the etch process modules (or from etch process module to etch process module) for plasma etch processing, and from there to the strip
inse process module, which also serves as the exit loadlock for this tool.
 Figure 3. Plasma descum for TFH fabrication creates a better resist profile. |
The important issues here are the increased robot arm deflection and end effector deflection observed when running TFH wafers. TFH substrates are thicker than silicon wafers and, in general, a TFH substrate has a greater mass than a silicon substrate of similar diameter. We had to confirm the reliability of the robot operation to ensure it would work with the additional substrate masses encountered with the TFH substrates. In this case, the simulated results were well within the normal operation window. Physical testing of the robot arm confirmed there was no deflection outside the safe operating zones.
 Figure 4. Plasma etch can pattern NiFe or FeN top pole films. |
Another critical component is the robot end effector. It is the device at the end of the robot arm that touches and supports the wafer. The end effector is typically the thinnest robot arm link, as it needs to fit between the cassette slots when loading or unloading the substrate from the wafer cassette. The additional TFH substrate weight caused the end effector used for silicon wafers to deflect outside the safe operating zone, leading to potential handling issues as it inserted wafers into or removed wafers from the cassette. We redesigned the end effector for less deflection by making it thicker (without compromising the "tight fit" problem) and by changing to a stiffer material than that used for silicon wafers.
The atmospheric robot moves wafers among the strip process module, the wet rinse station, and the exit cassette. This robot uses a vacuum end effector (rather than the gravity end effector used by the vacuum robot) that holds the wafer onto the end effector with vacuum to allow the robot to move very quickly without displacing the wafer.
Like the vacuum robot, both the atmospheric robot arm deflection and the end effector deflection needed verification.
The atmospheric end effector required redesign to accommodate the additional weight imposed by TFH substrates.
Square TFH substrates introduced another problem with the atmospheric robot design. The repositioning of the rinse station pins (needed to allow the rinse station to accept square, as well as round, substrates) interfered with the standard end effector geometry. A specially designed end effector could move the substrate from station to station without interfering with lift pins in the strip process module and in the wet rinse station.
Wafer alignment
The wafer aligner is the station on the cluster tool platform that corrects for potential wafer misplacement in the process modules (here plasma etch reactors) caused by original misplacement, or later movement, of wafers in the cassette. Prior to loading the wafer into any process module, the wafer is sent into the wafer aligner where it is rotated while sensors detect and mechanically correct the wafer position (from off-center to centered) and align the flat or notch in a predefined position (theta correction). Silicon wafers are round discs made with features (flats or notches) for defining theta. TFH substrates are not always round; even when they are, the substrates do not always have flats or notches. Thus, the wafer aligner used for TFH wafer transport required redesign to accurately position square substrates or round substrates without the aid of identifying flats or notches.
Plasma process module considerations
Wafers processed in plasma modules, either PECVD reactors or plasma etch reactors, are subject to temperatures that can be potentially detrimental to the electrical performance of the devices being fabricated. There is generally some thermal budget that must be adhered to in device processing. For example, when photoresist is used as a masking material, temperature excursions can reduce the photoresist structure to charred carbon. Also, when aluminum is used as an interconnect conductor, processing at elevated temperatures can cause unacceptable alloying behavior between aluminum and silicon. Of all microelectronic device fabrication processes, the magnetic materials used in TFH devices have some of the lowest tolerances to elevated processing temperatures. TFH makers specify the maximum processing temperatures as 200°C, 160°C, or even lower. High-density plasma etch reactors are usually built so that some radio frequency power (wafer bias power) is coupled through the wafer to the plasma so as to extract charged species from the plasma to aid in etch directionality. Some of this RF power will invariably contribute to heating the workpiece. This, along with the exposure of the device-side of the wafer to a relatively hot plasma, requires carefully managed heat transfer.
Additionally, plasma etch mechanisms that typically have chemical as well as physical components and nonuniform heating (or cooling) of the wafer can cause etch uniformity problems. (The same will also be true for single wafer PECVD reactors where temperature nonuniformity will lead to problems with film deposition uniformity.)
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Advanced plasma reactors are now built with electrostatic clamping modules, where DC electrical fields cause wafers to stick tightly to the chucking surface. Helium, flowing through the thin plenum formed by the chuck surface and the wafer back, maximizes heat transfer between the target wafer and the temperature-controlled chuck. These schemes, developed for thin silicon wafers with high electrical and thermal conductivities, need significant modification if they are to be applied to the thick wafers used for TFH devices, with their comparatively poor thermal and electrical conductivity.
Preventing damage: Corrosion and ESD
TFH devices can be less forgiving than silicon-based ones for their susceptibility to failures as a result of both post-processing corrosion and ESD. If a plasma etch process for TFH structures is based on chlorine (to take advantage of the high etch rates possible with chlorine-containing plasmas), then an effective means of preventing corrosion must be an integral part of the plasma etch process tool [3].
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Using combinations of plasma photoresist strip and DI water rinse treatments, we were able to successfully eliminate post-etch corrosion in the plasma etch of aluminum alloys on silicon wafers. In the photo on p. 122, an OEM rinse station integrated into a cluster tool platform is shown treating an etched (square) TFH device wafer.
Modifications to this rinse unit over its standard silicon processing configuration, developed jointly by the OEM supplier and the cluster tool manufacturer, centered around: 1) improvements to the rinse station fingers used to hold the TFH wafers, 2) new procedures developed to allow orientation of the rinser head for proper transfer of the variously shaped substrates, and 3) the previously described improvements to the robot arm end effector.
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GMR read/write heads can be extremely sensitive to damage from ESD. A lower threshold for silicon-based semiconductor component ESD damage is about 250V; GMR heads might succumb at 10V or less [4]. Static charges that are inconsequential to silicon ICs may have always existed, unseen, on processing tools that have already been extensively used in mass production, but they won't remain hidden for long after the first TFH wafers are processed and tested. OEM suppliers offer products that can be used for ESD abatement, and, once tool-specific mechanisms for building electrostatic fields are understood, processes can be modified to ameliorate the problem.
Conclusion
The thin film head industry can only continue to benefit from the synergy between IC processing and GMR read/write head fabrication (and vice versa — much of the electroplating technology used in advanced copper interconnects has its roots in TFH). Advanced photolithography tools using deep UV exposure wavelengths and processing techniques have been instrumental in allowing continued device shrinks in both fields. Plasma processes, both for deposition and for etch, also offer a means for wringing more and more performance from magnetic data storage devices.
Capital equipment vendors wanting to adapt silicon processing tools to TFH fabrication must be prepared to accept several challenges: transporting heavy, thick, possibly square wafers; managing plasma reactor conditions, particularly heat transfer, for a material with low thermal and electrical conductivity; and processing devices generally more sensitive to damage from electrochemical corrosion and electrostatic discharge. Some of these issues could be eliminated by industry consensus on wafer specifications. The others must be worked through as significant problems in tool design and engineering.
References
- Michael Biche, "Thin-film Head Lithography Overtaking Silicon," Solid State Technology, p. 89, September 1999.
- Robert Haavind, "The High Cost of 'Not Invented Here'," Data Storage, p. 5, May 1995.
- K.B. Jung et al., "Parametric Study of NiFe and NiFeCo High Density Plasma Etching using CO/NH3," Journal of the Electrochemical Society, Vol. 146, no. 6, p. 2163, 1999.
- David E. Swenson, Arnold Steinman, "Keeping Ahead of Electrostatic Discharge," Data Storage, p. 45, November 1999.
Paul Werbaneth is a graduate of Cornell University, and has worked in the semiconductor industry for 20 years. He is a staff process engineer at Tegal Corp., 2201 S. McDowell Boulevard, Petaluma, CA 94955-6020; ph 707/765-5608, fax 707/773-3015, email [email protected].
Sam Kirshman has a BSAE from Northrop Institute of Technology. He is a senior project engineer at Tegal, specializing in plasma reactor design and development.
Harry Slomowitz received degrees in electrical and chemical engineering from the City College of New York. He is a staff engineer at Tegal, presently managing customer-driven equipment modifications. He holds two patents related to semiconductor fabrication equipment.
Jim Thomas is a mechanical engineering graduate of Cal Poly-San Luis Obispo. He has 23 years of experience, the last 15 of which have been in the semiconductor capital equipment industry.