Advanced process control — the next generation
09/01/2000
Robert R. Anderson, Yield Dynamics Inc., Santa Clara, California
Yield management in the semiconductor industry has always focused on causal relationships between yield loss — or yield limitations — and the process. These have been the limitations inflicted by nonoptimized films, tool problems, and device design. For a new device, the goal of the analysis has been to move up the classic learning curve as quickly as possible to stabilize and maximize yields. Mature production will focus on maintaining the highest possible device yields. Electrical test yield fluctuations in a state-of-the-art logic facility can result in a loss of $500,000/week for a single point drop.
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RIGHT. Robert R. Anderson
Stable, single-process production simplifies the yield management task by allowing designs and tool usage to be monitored by trend charts and statistics. Foundries face a more arduous task in that the size of the total device production run can be as low as 200 wafers/mask set. Combine the rapid turnaround in mask designs with variations in the process, and the task of maintaining a stable, high-yield process can be daunting.
Recent yield management strategies
There are a number of companies offering yield management software today. Computer automation of tried-and-true methods has improved the engineer's ability to find the root causes of yield loss beyond the classic strip-back methods of failure mode analysis. Tools such as data mining and spatial signature analysis in combination with the huge production databases of WIP and electrical test have provided the yield engineer with powerful weapons in the competitive semiconductor fabrication arena. For the most part, these developments have come from young companies eager to enter the contest and grow independently of the parochial constraints of a single vendor's hardware interests or toolset.
Advanced process control
In what seems to be another isolated arena, there has been much recent attention in wafer fabs on the need for advanced process control (APC) methods to meet ever-narrowing margins. Unlike the traditional methods of statistical process control, APC implementations incorporate an analysis of the systematic errors by modeling past behavior of the process in order to predict future performance. APC performance prediction — and therefore correction — results in a more aggressive track in addressing the challenges imposed by future process margins. The reduction of process margins is, in turn, driven by thinner films, new materials, increasing levels of interconnect, and tighter specs for pattern lithography.
Today's devices incorporate sub-wavelength features. Once again, recognizing that optical lithography will be with us for at least the next five years, the industry seeks to improve production controls. These efforts are evident in the attention paid to them by research in APC methods. New techniques and products have arisen for production feedback and closed-loop controls.
As with any new idea, new software companies independent of the established mainstream of large corporations have spearheaded the effort.
Some APC concepts are embedded directly in the toolsets used in the fab, such as model-based APC systems used in tools for wafer film coating and exposure. Other APC methods have arisen to connect and control multiple process steps. One recent implementation involves advanced model and simulation methods for overlay and critical dimension processes. This system provides a means of extending mix-and-match optical lithography capability for the next two generations of devices down to 0.15mm design rules. Since APC in production involves linking a production sequence with a subsequent metrology sequence, these applications employ very large databases to maintain history and behavior.
Process yield vs. test yield
Historically, there has been little linkage between process and test yields. The forces of electrical yield run independently of those in the process to the extent that the yield engineer deals in units of "defects/cm2" rather than the pass/fail criteria of electrical test or response parameters of parametric test.
A few brave souls have conducted linkage experiments by biasing the lithography to fabricate known errors in the process. The lots were then electrically tested to empirically measure the electrical performance and yields of the lot.
From this information, critical device dimensions could be adjusted to optimize electrical access, clock speeds, and rise times. This method is powerful but time consuming, involves only one or two lots, and is not truly representative of the ever-changing process signature. Pioneers in these efforts have advanced without the benefit of focused analysis tools to ease their efforts and expand the scope of their understanding. The cost and difficulty of conducting these endeavors has restricted their efforts to the evaluation of single-point experiments rather than a concerted thrust involving a full DOE design surface to map out the interactions of even a snapshot of the elusive production interactions.
The future of our industry lies in the opportunity to take full advantage of information independently available in process and device test. An investment in analysis of this information will result in the ability to maintain high yields and bias the spectrum of devices to those with higher profit margins.
Facility-specific process design
Every production facility has a unique signature based upon its toolset selection and process implementation. Intel has used this fact in rigidly fixing their recipes for new sites. The logic or ASIC facility cannot enjoy this methodology by
the very nature of its rapidly changing product mix. Even the enlightened Intel approach, however, does not take advantage of the natural variations of the production cycle to map and track its elusive interactions.
 Yield Dynamics' Genesis yield management software enables IC manufacturers to isolate root causes of yield loss. (Photo courtesy of Yield Dynamics Inc.) |
The investigation of this signature represents an undiscovered opportunity in the industry. The results could influence the actual design of the device to use the natural capabilities of the target wafer fab. Some of the tools needed to determine the biases of design exist today, and they can be applied to data from electrical test, process, and lithography. These tools, with examples being those currently offered in our Genesis software, provide not only an ability to discover root causes of yield loss rapidly, but also to link the lithography database into an analysis of device performance using the customer's own electrical test databases. Future toolsets building on this framework will provide chip designers with the ability to fine tune their mask sets to the production signature of the target wafer fab, optimizing yields, product performance, and even production cycle time.
But don't expect these innovations to arise from the megalithic halls of today's hardware vendors. Look instead to new, agile software companies that arise and operate independently of the constraints imposed by the requirement that software support only one brand of hardware.
Robert R. Anderson is a co-founder of KLA Instruments, serves on the board of directors of several corporations and the board of trustees of Bentley College, and has also served as a member of NASDAQ's corporate advisory board. He is the chairman and CEO of Yield Dynamics Inc., 2855 Kifer Road, Suite 100, Santa Clara, CA 95051; ph 408/330-9320, fax 408/330-9326, e-mail [email protected].