Design and chip fabrication need to be linked
08/01/2000
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In the digital design world there have long been two camps, often separated geographically and rarely in contact with each other. One is the design camp, full of banks of workstations ablaze with color-coded chip layouts; the designers follow a set of design rules supplied by the fab to avoid such flaws as too little space between traces. The other is the semiconductor fabricating plant, where process engineers concoct the recipes that will turn the designers' conceptions into working silicon chips.
The buffer zone between the camps has been the translation service that converts the netlists put out by the design group into maskmaking software and checks for possible flaws in mask layouts. Designers and process engineers almost never talked to each other unless there was a problem. Since the design software checked for compliance to the fab's design rules, and verification software made sure the circuits would work as designed, there was almost never a problem.
That's all changing now. Circuit complexity is overwhelming the verification process, and the impact of physical design adds to the problem. Shrinking circuit features have gradually eroded design rule tolerances. The quest for higher-speed processors pushed timing requirements. Also, with faster clocks, the resistance and capacitance of narrower, denser interconnects began to disrupt timing. Some major designs passed verification, but then didn't work on first silicon, requiring months of redesign. Because time-to-market has become so critical for new chips, parasitic extraction has become an important step in finalizing designs and doing verification checks before a design is released to the maskmakers. As circuits move to subwavelength features and reticle enhancements become necessary, however, the link between design and fabrication has become even more important. Adding bulbs to corners and line ends for optical proximity correction may provide the needed wavefront engineering for lithography, but these new features may again change RC values, introducing new timing difficulties.
Intensive work is now going into encapsulating fixes for these effects into electronic design automation (EDA) software so that they can become part of the design process from early layout stages. Will that be enough? It could allow circuit designers and process engineers to continue rotating in their own orbits, but as circuit complexity continues to increase, it is unlikely to produce optimum circuitry. What will really be needed is a set of compromises based on mutual understanding of the potential and limitations of each discipline. That will be the only way that optimum trade-offs can be reached.
This is already happening in Japan. In the July issue of SST, an article translated from our partner Nikkei MicroDevices (AsiaFocus, page 62) showed how circuit problems could actually be alleviated by developing some novel structures on a chip. Such solutions are coming from collaboration among designers and process specialists in vertically integrated Japanese electronics companies. Japan sees this as a way to gain an edge over its foreign competitors. In Europe, Philips design engineers manipulate circuits on workstations right in the Crolles fab of STMicroelectronics (a competitor to Philips on some types of chips!), so they are close to the fab engineers who must implement their designs.
Some years ago in the US, DARPA (Defense Advanced Research Project Agency) conceived of a research program to explore the possible interchange between circuit CAD and TCAD to develop optimum trade-off capabilities. Instead of pursuing this program, the electronics group at DARPA plunged into a major program on low-power electronics. They saw that lightweight, highly functional electronic equipment provided military forces with a big future technology advantage. That made good sense, but the need to link EDA and TCAD has not gone away. In fact, it will become ever more critical.
The sooner designers and process engineers learn to communicate with each other, the better the complex chips of the future will perform. The time is now.
Robert Haavind Editor in Chief