Applying a thin imaging resist system to substrates with topography
08/01/2000
M. Neisser, Arch Corp., N. Kingstown, Rhode Island
G. Grozev, Arch Corp., Zwijndrecht, Belgium
M. Maenhoudt, M. Lepage, H. Struyf, IMEC, Leuven, Belgium
overview
A bilayer resist system consisting of a thin, silicon-containing imaging layer over a planarizing, reflection-suppressing underlayer gives better patterning performance than a single-layer resist/thin antireflective coating system, especially in dual-damascene applications with high topography.
 Figure 1. TIS-2000 process flow with a thick planarizing underlayer and a silicon-containing imaging layer (blue). |
Photolithography and photoresist technologies have evolved to make smaller and smaller devices. Tool technology has progressed to successively shorter exposure wavelengths and higher numerical aperture (NA) lenses. This approach has increased the resolution capability of exposure tools but reduced the intrinsic depth of focus (DOF) of the aerial image. Semiconductor processes have evolved to accommodate some of this reduction. In particular, chemical mechanical polishing (CMP) — and processes that take advantage of this capability — have provided basically flat substrates for critical-level lithography.
The minimum feature sizes of metal levels and vias have also shrunk along with decreases in the minimum feature sizes on critical levels. However, the advent of dual-damascene interconnect processes has meant that topography is getting worse instead of better as metal-level dimensions shrink. This is different from past technology evolution, where topography either improved or stayed the same. The difficult substrate topography involved in dual damascene is thus a new type of lithographic challenge [1].
At IMEC, work is underway to develop a copper dual-damascene process, while at Arch Chemicals, we have developed a thin imaging photoresist system called TIS-2000 designed to accommodate difficult substrate topography [2]. We have found that the TIS-2000 system has great potential for solving difficult process integration problems such as those involved in dual damascene.
TIS-2000 process flow
The TIS-2000 process flow appears in Fig. 1. First, a thick (typically ~500nm) underlayer is coated over the substrate. The process conditions are similar to those for a bottom antireflective coating (BARC), but the material and purpose are somewhat different. The underlayer has a high-enough absorbance to suppress substrate reflections, but not so high as to create strong standing waves in the imaging layer [3]. A thin imaging layer is then coated on the underlayer, with a typical thickness being 235nm. The imaging layer functions just like a resist, except that it contains a significant amount of silicon, which gives it etch properties different from those of a typical resist.
 Figure 2. Comparison of a) a thin imaging and b) a SLR with BARC when both are coated over a substrate with topography. |
After the imaging layer is exposed, baked, and developed, a dry (plasma etch) develop step transfers the pattern in the imaging layer into the underlayer. The silicon in the imaging layer makes it possible to do this dry develop step with high selectivity. Once the underlayer is etched, it is ready to act as a barrier for substrate etch. Since the underlayer is organic and has no silicon content, it etches like a standard resist, except that its etch resistance is higher than most single-layer resists (SLRs). This higher etch resistance is possible because the material has been optimized for that property and does not have to make compromises in etch resistance in order to build in photosensitive behavior [4]. For example, the TIS-2000 underlayer etches at about half the rate of a reference deep UV resist in a polysilicon etch plasma.
Advantages
This thin imaging system has a number of advantages over a standard "single-layer" process for application over topography. Figure 2 shows a comparison of the two approaches. In the SLR system, the BARC has to be thin relative to the photoresist layer. Otherwise, one cannot etch the antireflective coating (ARC) and retain enough photoresist to protect the substrate. The result is that the photoresist accommodates most of the topography, creating thickness and/or height variations in the photoresist layer. These height variations consume the usable DOF of the exposure tool in the single-layer system.
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In the thin imaging system, the imaging layer thickness is uniform in spite of substrate topography, because the underlayer planarizes, resulting in a higher usable DOF. Likewise, depth variations in a single-layer system make it harder to clean out the bottoms of exposed features, and also lead to CD variations that depend on the local thickness of resist. For example, residual swing curve and bulk absorption effects will make a trench in the shallow part of the resist a different size than a trench in an area where local topography makes the resist thicker. These different printed sizes will reduce the overlapping process windows for all the trenches.
A thin imaging system does not suffer from this defect.
The local thickness variations in BARC and photoresist thickness also make it harder to suppress reflectivity variations. Thickness variation in underlying oxide across the wafer causes swing effects, and it has been reported that single-layer ARCs are inadequate to suppress them [5]. Resist and ARC thickness variations caused by topography only make matters worse. The underlayer of a thin imaging system is thick enough and opaque enough that all effects of underlying oxide thickness variations are suppressed [6]. Swing curves from imaging layer thickness variations will be small, because the standing wave in the imaging layer is so weak. The bottom line is that a thin imaging system will have much better swing behavior than a SLR even with a BARC.
The table shows how a thin imaging system can provide excellent lithographic process windows for trenches (spaces [s]) and for lines (l). Contact hole process windows have also been reported recently [7]. Because of the planarization by the underlayer, the usable imaging-layer process window over topography will be the same as that measured for flat substrates.
Process integration
The challenge of implementing a thin imaging system is not in lithography, but in process integration. The underlayer etch process is considerably different from a BARC process and needs to be optimized for etched profile, for imaged-to-etched size bias and for after-etch process window. We believe that the work of integrating TIS into a process flow will be repaid with a robust and extendable process. Our experience so far with a via-first dual-damascene process has been that the TIS-2000 resist system adapts itself naturally and easily to substrates with topography.
 Figure 4. SEMs of cleaved dual-damascene wafer structures before exposure with a) vias filled, b) after wet development, c) after partial, and d) full underlayer etch. |
Figure 3 shows a possible via-first dual-damascene process flow. First, a layer of dielectric with an embedded etch stop is deposited (Fig. 3a). The stack is thick enough (1.0-1.5µm) for both a via level and the corresponding metal level. Then photoresist is applied, exposed, and developed for the via pattern (Fig. 3b), which is subsequently etched all the way through the dielectric (Fig. 3c). A new layer of photoresist is then applied and patterned in a trench pattern. Usually a partial fill of resist or ARC is left in the bottom of the via after resist development. This material can be used as a barrier during trench etch (Fig. 3d). A trench etch is then done, which etches down to the embedded etch stop to create a two-level structure. After resist strip and surface preparation, the metal is deposited (Fig. 3e) and a CMP step completes the dual-damascene process to give a unified metal and via level (Fig. 3f).
 Figure 5. Depth of underlayer etch as a function of time. Etch depth includes the depth of underlayer in the vias plus the 350nm on top of the vias. |
In a typical SLR process, the BARC will partially fill the vias and remain in place during trench etching and be removed later. The BARC prevents the resist from going too deeply into the vias, where it might not be exposed enough to develop. For this BARC fill to be successful, the depth to which the vias are filled by the BARC must be well controlled all over the substrate, no matter what the density of the vias. Optimizing the BARC fill of damascene vias is difficult and often requires considerable process development and materials testing [8]. It is possible to fill vias of different pitch equally by careful selection of the right BARC and coating conditions, but this only works if all the vias are the same size. A new BARC optimization has to be done for each via diameter.
For a thin resist system, the first integration issue is how well the underlayer will really planarize when coated over etched vias. Figure 4a shows a cross section of underlayer coated over an array of 250nm vias. The vias are completely filled and the top of the underlayer is flat without any topography caused by the vias underneath. The thickness of the underlayer over the substrate in the via region is about 350nm, which is enough to insulate the imaging layer from any optical effects caused by substrate reflections. Figure 4b shows a similar array of vias after the imaging layer has been exposed and wet developed. The trenches in the substrate areas without vias also imaged cleanly but are not shown.
The next step is the underlayer etch. Depending on the process integration scheme, one may want to remove all the material from the vias or leave a certain depth of underlayer in them. In either case, it is important to be able to control the depth of the etch. Given that there is 350nm of underlayer above the top of the vias, and the filled via depth is 1.2µm, anywhere from 950-1550nm of underlayer must be etched using the 235nm-thick exposed imaging layer as the mask. Figures 4c and 4d show the profiles after partial and full etch of the vias, and Fig. 5 shows total etch depth as a function of time. The etch depth shown in Fig. 5 is the depth etched into the vias plus the extra depth of underlayer above the top of the dielectric. The underlayer etching used an O2/SO2/He type of process. Note that some of the underlayer plugs can fracture, fall out, or stay with the other half of the cleaved wafer during cross-sectioning to produce figures like Fig. 4c. This is why not all the vias look half full in Fig. 4c. Although not shown here, the same etch cleared trenches in areas without vias down to the top of the dielectric without damaging the wall profiles.
It is clear from Fig. 5 that the etch depth in vias is a linear function of etch time, allowing good control. The cross sections show that the etch selectivity between imaging layer and underlayer is sufficient to maintain clean trench profiles in the underlayer above the tops of the vias even with an underlayer etch to the bottom of the vias, a total underlayer etch depth of 1550nm. This is more than six times the critical dimension of this level, a ratio we believe would be impossible with conventional SLR.
The substrate is now ready for a trench etch using the remaining underlayer as an etch mask in order to produce the dielectric profile in Fig. 3e. Given that the depth of underlayer, if any, remaining in the vias can be controlled by etch time, we are now studying process options that require a variety of via fill depths to demonstrate the flexibility of the TIS-2000 system.
In conclusion, we have shown that a thin imaging resist system can provide excellent lithographic process windows at 180nm and below. Our expectation is that this sort of resist system will provide a process benefit in most situations where there is difficult substrate topography. In particular, we have shown that the underlayer planarizes over the deep vias characteristic of a via-first dual-damascene process and can be fully or partially removed by dry etching with the imaging layer used as the etch mask. A 193nm TIS system is already available and work is progressing on a 157nm system, so this sort of process should be extendable to smaller geometry features and shorter exposure wavelengths.
Acknowledgments
We would like to thank Kurt Ronse, Ivan Pollentier, Murrae Bowden, Plamen Tzviatkov, Thomas Sarubbi, and Serge Vanhaelemeersch for valuable discussions; and Diziana Vangoidsenhoven, John Biafore, Veerle Van Driessche, and Frieda Van Roey for their assistance in the experimental work.
TIS-2000 is a trademark of Arch Chemicals Inc.
References
- Single damascene processing can provide polished substrates for each new level, but cost considerations and, perhaps, reliability and cycle time make dual damascene preferable.
- P. Foster et al., "Advances in Resist Technology and Processing XVI," SPIE, 3678, p. 1034, 1999.
- M. Neisser et al., Proc. SPIE 25th Annual Microlithography Symposium, 4000-98, in press, 2000.
- As imaging wavelengths have shrunk, it has become harder and harder to put both etch resistance and high-resolution imaging into the same material. See, for example, R.R. Kunz et al., "Limits to Etch Resistance for 193-nm Single Layer Resists," Proc. SPIE, 2724, p. 365, 1996.
- J. Yu et al. have reported that a single layer of BARC is inadequate to suppress swing curves over transparent films like oxide that vary in thickness across a wafer. J. Yu, "Quarter and Subquarter-Micron DUV Lithography with PECVD ARL: Application and Restriction," Proc. Interface '97, Keystone Communications, Fremont, CA, p. 259, 1997.
- M. Neisser et al. discusses this issue in detail.
- W.D. Kim, S. Hwang, G. Rich, V. Graffenberg, Proc. SPIE 25th Annual Microlithography Symposium, 3999-111, in press 2000.
- See for example, B. Simmons et al., Proc. Interface '99, Kirkpatrick Communications, San Ramon, CA, p. 183, 1999.
Mark Neisser graduated in 1981 from the University of Michigan, Ann Arbor with a Ph.D. in chemistry. He worked for the International Business Machines Corporation from 1981 until 1998, where he held a variety of positions in packaging and semiconductor research and development. In 1998 he joined Arch Chemicals, where he is Manager, Advanced Technology Development in the photopolymers division. He is the author of over 20 technical publications and 8 patents in the fields of chemistry, lithography, photoresist and semiconductor packaging materials.
Grozdan Grozev received his MS degree in solid state physics from Sofia University, Bulgaria. For ten years he worked in the Institute of Microelectronics, Sofia. He joined IMEC, Belgium, in 1995, where he worked on advanced i-line. Grozev has been a member of the Advanced Process Development Group at Arch Chemicals since 1998.
Mireille Maenhoudt received her PhD in physics from the Catholic University of Leuven, Belgium, in 1995. After a post-doc on nanolithography at the same university, she joined the lithography group at IMEC in 1996. Her main topics of research have been CD control of DUV steppers and scanners, lens aberrations, and simulations. She has been involved in dual damascene process development for metal and interconnect layers since last year.
Muriel Lepage received a degree in civil engineering (specialization: polymer chemistry) from the University of Liege in Belgium in 1998. Since she joined Imec in the same year, her work has mainly been focused on the development of oxide and low-k patterning applications, for damascene in particular.
Herbert Struyf joined Imec in 1998, after receiving his Ph.D. in Chemistry from the University of Antwerp in Belgium in 1996. He started working in the field of dry ozide and nitride etch. His primary topics of development for the last two years have been etch and strip of low-k materials for damascene applications.