Technology News
07/01/2000
Sematech evaluations show promise for porous
Porous extra low-k (XLK) dielectrics are undergoing extensive evaluations at Sematech, and so far the results are promising. Porous materials are likely to be needed to continue the reduction of the dielectric constant of interconnect dielectrics, and they are an attractive option because a given material has the potential to offer a progressively lower dielectric constant by increasing the porosity, rather than changing the material. The work by Changming Jin and Jeff Wetzel of Sematech presented at the International Interconnect Technology Conference (IITC) in June demonstrated the feasibility and good performance of a spin-on Dow Corning XLK film based on an HSQ resin.
 Figure 1. Cross-section SEM images of 0.35mm Cu damascene lines in a porous extra low-k dielectric. (Courtesy of Sematech) |
A thorough materials property characterization included dielectric constant measurements with a metal-insulator-metal structure formed by depositing Al dots on an XLK film deposited on a heavily doped Si substrate. It was measured to be 2.19 ±0.10. The film passed adhesion tests, and the porosity was measured to be 59.5% by small angle neutron scattering (SANS). The pore connectivity was 100%, which was also measured by SANS, and the density was 0.88g/cc. In a thermal stability test, no defects were observed after a 400°C 1 hour anneal of the XLK film with CVD SiO2 caps.
Integration studies were conducted with one-level metal Cu damascene structures, as shown in Fig. 1. The results indicate that there are solutions to the concerns about the mechanical and chemical integrity of porous films. One conclusion derived from FTIR measurements of a SiHx integrated area at different points in the process was that an O2-free ash process is needed to minimize the damage to XLK films. The CMP results were mixed. A blanket XLK film failed a CMP test, which was expected because of the downward and shear stresses applied to the porous material. However, CMP tests on patterned films resulted in no delaminations or other defects. More study is needed to understand the details of the structural behavior here.
 Figure 2. Cross-sectional TEM and EDX analysis of the barrier integrity of the Cu/XLK structure. No Cu diffusion into the dielectric was observed. (Courtesy of Sematech) |
Electrical tests showed that post-passivation annealing steps can eliminate the negative effects of CVD Si3N4 deposited on the surface of the structure. After deposition of the nitride, the capacitance between lines increased because the nitride replaces air in the dielectric immediately between the Cu lines. One thermal annealing cycle at 400°C decreased the capacitance to levels even below the values before the passivation. A second annealing cycle improved it a little bit more. The XLK films probably also contained some moisture that was driven out with the annealing.
Leakage current distributions of the test structures were also measured, and these improved with thermal cycling as well. This was probably due to a decrease in moisture. As shown in Fig. 2, TEM and EDX results show that the Cu/XLK barrier integrity was good, so there was no diffusion of Cu into the XLK that would cause a permanent increase in the leakage current. — J.D.
Motorola demonstrates universal memory technology
Motorola Labs and the company's DigitalDNA Laboratories of the Semiconductor Products Sector have demonstrated a revolutionary memory chip that will potentially replace today's semiconductor memory technologies. It is a 3V nonvolatile magnetoresistive random access memory (MRAM) with an address access time <15nsec; initial data of several billion read-and-write cycles indicate the potential for unlimited endurance. This "universal memory" will allow the integration of multiple memory options within one chip enabling faster, lower power, less expensive solutions for next-generation wireless products. (Some of this development work was funded by DARPA.)
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Previously, Motorola engineers had reported, at the IEEE International Solid State Circuits Conference in February, on a MRAM test chip with an address access time of 24nsec and cycle time of 34nsec. In April 2000 at the IEEE International Magnetic Conference, the company's engineers reported an address access time of 14nsec and a cycle time of 24nsec using only 0.6mm geometry.
Motorola's MRAM cells are based on a single transistor and magnetic tunnel junction (MTJ) structure (see figure) in which the MTJ is integrated on top of the transistor to achieve a small cell size. This provides an extremely cost competitive memory. The fast read-and-write speed combined with unlimited read-and-write cycles and competitive cost will enable MRAM to replace Flash, DRAM, and all but the fastest SRAM.
Targeting MRAM as part of its embedded system-on-chip solutions, Motorola sees MRAM as an advantage for many future applications. The speed and low power characteristics of MRAM will enable one-chip solutions for next-generation portable devices including wireless applications, organizers, appliance electronics, automotive electronics, laptop computers, and consumer electronics. The system-on-chip approach will mean better performance through faster processing speeds and eventual lower costs.
Since MRAM is readily integrated with conventional CMOS, single chip solutions will considerably reduce the cost of current multichip memory-processor applications and substantially increase the speed of data downloads into memory from the web. In applications where speed of microprocessors is limited by the bottleneck of data transfer between memory chips and processor chips, MRAM removes the bottleneck by placing the memory directly on top of the microprocessor.
Peter Gill, VP and director at the Materials and Structures Laboratories of Motorola Semiconductor Products Sector, says, "The smart phones of tomorrow will require increased memory. This means that local, on-chip memories capable of communicating with multiple processor configurations will be needed to provide better performance and lower power. In addition, MRAM is nonvolatile and is expected to meet commercial and industrial temperature requirements. To the consumer, this means exciting new possibilities such as real-time wireless video."
According to Herb Goronkin, VP and director, Physical Research Laboratories, Motorola Labs has demonstrated a small test chip that is fully integrated. "We've demonstrated full integration of MTJ with standard low cost CMOS circuitry and have been able to achieve exciting performance characteristics. In addition, we have made significant progress toward increasing the signal from an MTJ cell and reducing the resistance of MTJ-based material. The current resistance levels are ideal for our memory architecture. We have been able to achieve these parameters uniformly across 150mm wafers."
MRAM is expected to offer significant performance advantages compared to existing memory technologies. It is expected to have better write characteristics because it does not require high-voltage tunneling required for nonvolatile Flash. And, it will offer instant-on capability, eliminating the lengthy boot times for computers and other electronic devices. MRAM is also expected to substantially reduce the battery power drain for portable devices because it does not require background refreshing of DRAM. Motorola officials expect products incorporating MRAM technology within a few years.
CVD tungsten extends MEMS lifetime by order of magnitude
The exposed surfaces of silicon-based MEMS devices take a beating during operation. MEMS devices are typically composed of polycrystalline silicon, in part because of the processing history and infrastructure that exists from the IC industry. Polysilicon, though, is not particularly wear resistant, and this is a concern in MEMS devices with polysilicon components that move and come in contact with each other.
Researchers at Sandia National Laboratories are developing a solution to the problem of surface wear in MEMS devices that, like many successful MEMS processes, takes advantage of the existing IC equipment base. They have found that a CVD coating of tungsten extends the lifetime of MEMS devices by about an order of magnitude, and they have also demonstrated some key traits that make CVD tungsten an excellent process for integration into a MEMS process flow.
These findings from S.S. Mani and co-workers at Sandia were presented at the IEEE 38th Annual International Reliability Physics Symposium in April in San Jose. CVD tungsten has several processing characteristics that meet the needs of a protective coating on polysilicon. It can be selectively deposited on silicon at a relatively low temperature (<450°C) by the following two reactions: 2WF6 + 3Si --> 2W + 3SiF4 and WF6 + 3Si --> W + 3SiF2.
It is a self-limiting process — the process essentially stops once the surface is coated with W — so thin layers can be made very consistently. It is conformal, and since the deposited tungsten is about half the thickness of the consumed silicon, the tungsten can be deposited into the smallest gaps. This trait also allows it to act as a release layer, creating a space between adhered parts. The tungsten adheres well to polysilicon and is very hard.
Figure 1 shows a microengine that has been used to study wear resistance in many MEMS evaluations. Without the W coating, the median time to failure is 400,000 cycles. With the W coating, there were no failures at 2,000,000 cycles, at which point the test was stopped. Figure 2 shows a cross-section of a polysilicon gear's pin joint after cycling of parts with and without the tungsten coating. There is a dramatic visual difference in wear resistance, and the device shown with the W coating shows essentially no wear after 1,000,000,000 cycles.
The effect of adding a thin film with different properties from the polysilicon base is a concern, but significant problems are not expected because the W layer is relatively thin (~15nm). Studies of the mechanical behavior of thin tungsten films on the polysilicon MEMS structures are underway. Preliminary results show that the bending stiffness increases by about 2%, and the resonant frequency of a structure decreases by about 4% because of an increase in the mass of the structure. These are not significant problems, and they could be taken into account during the design. The mechanical evaluations are continuing.
Other materials that have been tried for MEMS protection lack one or more of tungsten's key features. PECVD Teflon reduces friction very well, but it is not hard, and its long-term behavior in this application is unclear. Polymers have been used, but they are not compatible with the high temperatures of the packaging processes, and their behavior inside a high-vacuum package is a concern. Diamond and silicon carbide are attractive because of their hardness, but they are less likely to be cost-effective because they do not leverage IC tools sets as well as CVD tungsten.
157nm litho gains momentum
For a technology option that had been all but dismissed less than two years ago, 157nm lithography is gaining remarkable attention, and if a recent flurry of 157nm activity is any indication, the chances that it will enter full production at the 70nm node appear to be improving. International Sematech's symposium on 157nm lithography (held May 8-11 in Dana Point, CA) was expected to pull in more than 300 attendees; more than 60 abstracts discussing new developments in 157nm technology were submitted. "I'm really impressed," noted Rich Harbison, conference chairman, adding that the event has drawn more enthusiasm than any of Sematech's early 193nm symposiums held several years ago.
"157 is moving fast and furious," said Jim McClay, VP of SVG Lithography's 157nm program. Just days before the symposium, SVGL, Wilton, CT, unveiled a 157nm mini-scanner on a modified Micrascan III+ platform. McClay said the company has orders for both 157nm mini-scanners and full-field systems. Full-field development systems are slated for delivery in the first quarter of 2002, with production systems following in 4Q02.
The 0.75NA mini-scanner, which features a 4mm x 22mm scan field with overlay capability, can be used for early product development in addition to providing a vehicle for resist and reticle development, said McClay. It also allows SVGL to demonstrate critical system issues, such as purging and contamination. The system features a variable 6x reduction ratio but the full-field step and scan system will have a 4x reduction ratio, and a larger 26mm x 34mm field. The production system also will use SVGL's new VHNA (very high numerical aperture) common platform bridging 248nm, 193nm, and 157nm systems; the footprint will not change.
Meanwhile, DuPont Photomasks said it has been awarded a contract by International Sematech to develop a pellicle that can be used in conjunction with 157nm lithography. The challenge is to develop a polymer for pellicle use that won't absorb light projected at 157nm. Under the contract, DuPont will work with its former parent company, E.I. DuPont de Nemours and Company, to develop the pellicle over the next 18 months; in preliminary work, the two companies have produced ultra transparent polymers suitable for use in 157nm lithography.
In other litho developments:
- Germany's Infineon Technologies has joined the three-year old EUV-LLC, which was founded by Intel, Motorola, and AMD to develop extreme UV lithography. The chipmaker also is participating in the European MEDEA project to develop ion projection lithography.
- SVGL has proposed standardization of a removable pellicle for EUV reticles. Conventional pellicles cannot be used in an EUV system; under SVGL's proposal, the pellicle would only be removed from the reticle during exposure, said Noreen Harned, head of SVGL's EUV program.
- SVGL says 193nm equipment buys have begun in full force, with Conexant, Cypress Semiconductor, and Lucent Technologies topping off the latest round of 0.6NA and 0.75NA system buys. Samsung, Hyundai, and Intel have also placed orders. John Shamaly, SVGL president, says the orders "were won on technology. We'll get the follow-on orders." SVGL officials believe 193nm lithography will be in full production in 2002. Adds Papken der Torossian, CEO of Silicon Valley Group, "There's a tremendous shortage of advanced capacity [below 0.18mm]. We're under tremendous pressure ... we're changing our forecasts weekly." —C.L.
Several companies targeting friendly cleaning replacements
Several leading semiconductor manufacturers in the US and Europe, including Philips, have teamed with FSI International to develop environmentally friendly wafer cleaning and resist stripping process technologies. This work is focusing on FSI's patented ozone-based DIO3 cleaning process as a means to reduce the use of harsh and more costly chemicals, such as the sulfuric-peroxide mixture or Piranha in photoresist stripping and RCA in cleaning (see figure).
Don Mitchell, president and CEO of FSI, notes, "Chemicals such as H2SO4, H2O2, and NH4OH require extensive neutralization at disposal, a very expensive process, especially in Europe where environmental disposal regulations are particularly stringent." According to Mitchell, reducing chemical usage not only provides positive environmental outcomes, but also results in cost savings as well. "Manufacturers can expect savings in chemicals of $100,000/year in a fab with 20,000 wafer starts/month; this averages 4-6 cents/wafer in savings, depending on the process recipe being used," he says.
Philips has been using FSI's supersaturated DIO3 system since August 1999 in its Eindhoven research facility for front end of line (FEOL) and back end of line (BEOL) photoresist strip and FEOL critical cleaning. This R&D installation has been used to demonstrate to other Philips production fabs the cost saving of the DIO3 process. Through lower chemical and water usage, Philips expects to positively impact its COO and show a return on its investment in new cleaning equipment.
Working with another leading European semiconductor manufacturer where DIO3 is already used in production, FSI and the customer are developing "new recipes in the area of low-cost pre-diffusion cleaning."
In other work, a joint development program between International Sematech, AMD and FSI, DIO3 is being evaluated in AMD's Sunnyvale, CA, facility for FEOL resist cleanup. "This project is targeted to eliminate the use of Piranha from photoresist cleanup," said Phyllis Pei, International Sematech ESH program manager. "It is through joint development programs of this kind that our members become aware of processes that may result in environmental benefits." — P.B.
Semicon Singapore: Strength in Asia-Pacific's backend industry
The worldwide boom in the semiconductor industry was reflected recently at the Semicon Singapore 2000 Test, Assembly & Packaging Show. All available exhibit space was sold out to approximately 600 exhibitors and a record number of more than 8000 attendees at the show held May 9-11 at the Singapore International Convention and Exhibition Center in the Suntek City complex. In addition to the exhibits, a variety of technical, market and educational programs and events were held, including market trends in CSPs and BGAs and the 4th Annual Test, Assembly & Packaging Automation and Integration Conference.
Semiconductors account for roughly 2% of Singapore's gross domestic product, and local industry growth of about 22% outpaced the world average last year. Most of the major players in the semiconductor industry operate backend facilities in Southeast Asia, thereby attracting many equipment suppliers. Semiconductor companies in the Asia-Pacific region are investing up to 40-50% of semiconductor revenues in capital purchases.
Many exhibitors ranked the show second or third in importance after Semicon West. "It's not the semiconductor industry alone but also the cosmopolitan atmosphere and the geographic location that make Singapore an attractive meeting point," noted C.L. Beusch, account manager for the Swiss process equipment man'facturer Balzers Instruments. Balzers presented a turnkey solution for 'soft' hydrogen plasma cleaning for bonding and molding. After processing times of only 5-20 minutes, the cleaning effect lasts more than one week. The low-energy plasma source is a joint development of Balzers Instruments and the University of the Federal Armed Forces, Germany.
Prominent on the show floor was Kulicke & Soffa showing its new line of automatic ball bonders that offer increases in productivity without the need for process requalification. K&S recently announced record bookings, sales and net income for the second quarter of FY 2000, which ended on March 31.
Also present at Semicon Singapore, ESEC showed its wire bonder model 3088, which is an ultrafine pitch platform with the widest bond range in the IC industry. Compared to the previous year, sales of the Swiss supplier have grown by 56% to SFr448 million (about US$250 million), thereby leading the worldwide market for die bonders. ESEC Asia-Pacific has recently embarked on an expansion program for its local R&D center.
Although Teradyne and Agilent were notable by their absence, other test equipment makers, such as Advantest, had a significant presence at the show. According to an Advantest spokesman, growing IC complexity is causing test costs and test times to rise disproportionately. Test costs of some devices already account for as much as 30% of total production cost. Closer cooperation between IC vendors, EDA vendors, design centers and the ATE industry is necessary to respond to the increasing technological and economic demands of the IC market. — Achim Strass, Contributing Editor
Litho update: 5x reduction ratio on table
The industry likely will begin exploring an increase in photomask magnification to 5x from today's 4x reduction ratio, following a recent meeting of lithography experts who expressed a preference for increased magnification at the 70nm node.
The 5x consensus for the 70nm node was reached among a group of 62 participants in International Sematech's second annual Stepper Reduction Ratio Workshop held in conjunction with the consortium's 157nm symposium in Dana Point, CA. For the 100nm node, the majority of attendees preferred maintaining the 4x ratio, noted Gerhard Gross, International Sematech director of lithography.
A shift to a 5x ratio is aimed at easing development of an overall optical litho solution at the 70nm node, and would not require a change from the current 6-in. reticle size. An alternative increase to a higher 6x reduction ratio would require an accompanying shift to a larger reticle — from the current 6-inch reticle size to a 7- or 9-in. reticle, notes Gil Shelden, workshop chairman and manager of Sematech's optical extension program. A move to 9-in. reticles had been envisioned in recent years, though a variety of factors has delayed their adoption, including slower growth in die sizes and the cost of developing new infrastructure, which some have likened to the transition from 200mm to 300mm wafers. "I don't see us going to 6x, 9-inch. What we're trying to gain with 5x is time," Shelden said.
This year's meeting also concluded with a consensus to decrease scanner field size from 26mm x 33mm to 22mm x 26mm.
At the first reduction ratio workshop held last year, the lithography experts recommended maintaining a 4x ratio, but Shelden indicated that last year's meeting kicked off numerous discussions on the issue. "There are now a lot of people getting used to the idea," he said, noting that the next few months will serve as a digestion period for the industry — specifically at stepper suppliers, lens suppliers and chipmakers — to further examine the 5x issue. Shelden hopes to see some firming of plans within a year. "If consensus holds, and we go to 5x, then the first place I'd see it impacting is the 157nm tools or the very high NA [0.8] 193nm tools."
Stepper supplier ASM Lithography is said to favor a 5x shift, and according to sources at the 157nm symposium, the company's 157nm system will incorporate a 5x reduction ratio. Canon already offers 5x systems. Officials from the firms could not be reached for comment at press time.
Nikon prefers 4x but would support 5x, said John Wiesner, senior VP of engineering. SVG Lithography, however, plans to maintain the 4x ratio. "We have customers demanding 4x," said Jim McClay, VP of SVGL's 157nm program. "It'll be the customer community that will drive what takes place." SVGL is planning to introduce a full-field 157nm system in late 2002, in time for early 157nm insertion at the 100nm node in 2003.
"At 100nm we know there will probably be two different reduction ratios offered by two different suppliers," said Sematech's Gross.
McClay and Gross were just two of roughly 300 attendees at the 157nm symposium held May 8-11. "It was one of the biggest 157 events I've seen," McClay commented. "It's amazing how fast this is moving."
Presentations at the 157nm gathering disclosed a number of developments in potential show-stopping areas, including with resists and pellicles; overall the meeting was upbeat, with attendees gaining confidence in the feasibility of 157nm lithography. Still, Rich Harbison, symposium chair and 157nm program manager at Sematech, says he'll be surprised if the industry doesn't uncover additional hurdles in 157nm development. "There's no slam dunk whatsoever," he said. "The biggest issue we have now is insertion timing."
IRPS 2000: Gate oxide breakdown mechanisms detailed
The increasing body of evidence in the critical area of gate oxide breakdown is altering the accepted view of the mechanism of oxide failures. Several teams of researchers presented their latest work at the IEEE 38th Annual International Reliability Physics Symposium in San Jose, CA, and much of the independent work points to the same set of conclusions.
The prevailing model describing gate breakdown had been the "E-field model," in which the strength and duration of the electric field across the gate are responsible for failures. One of the problems with this theory (and the driving force for much research) has been the "polarity gap," where experiments show a dependence of the breakdown in thin (<5nm) oxide films on the sign of the electric field. This model does not account for that.
The competing view has been a model in which the breakdown is driven by the voltage, not the electric field. Paul Nicollian of Texas Instruments Silicon Technology Development (Dallas, TX) presented strong evidence for this and demonstrated that the E-field model is physically incorrect. Breakdown is a result of the maximum — not the average — electron energy at the anode, so the voltage, not the electric field is the key parameter.
Jonathan McKenna of IBM (Essex Junction, VT) provided another set of data supporting this finding, using experiments with different levels of doping in p+ polysilicon gates. The charge-to-breakdown (QBD), which is related to the voltage, is the physical parameter most closely correlated to breakdown, not the time-to-breakdown (TBD) as suggested by the E-field model.
Another area of debate that was clarified was the physical mechanism causing oxide breakdown. The two main theories that have been proposed are hydrogen release and anode hole injection. Hydrogen release is the process by which energetic electrons break Si:H bonds at interfaces, thus weakening the oxide. With anode hole injection, tunneling electrons release energy when entering the anode and create energetic holes that get injected in the gate oxide and cause breakdown.
Nicollian of TI presented some other work demonstrating that anode hole injection is likely to be the significant mechanism. He showed that bulk traps in the oxide, not interface traps, are responsible for breakdown. This was done by measuring stress induced leakage current (SILC), in which tunneling through bulk traps is independent of the sense voltage, but tunneling through interface traps does depend strongly on the sense voltage. He also showed that anode hole injection increases the generation rate of bulk but not interface traps, so this supports anode hole injection over hydrogen release as the primary mechanism. Nicollian did say, though, that there are effects that are not addressed by anode hole injection, so more needs to be understood. He also pointed out that the relative importance of bulk and interface traps could change as oxide thickness is scaled.
Muhammad Alam of Lucent Bell Labs (Murray Hill, NJ), whose work also confirmed that oxide breakdown is voltage driven, used an improved anode hole injection model to explain many of the issues, and his results provided an optimistic view. The improved models match the existing data better than previous models, and when these are extrapolated to ultrathin oxides (1.5-2nm), the results show these films to withstand higher voltages than the linear extrapolations of other models indicate. The key concept is that at lower voltages, tunneling electrons produce fewer holes, and since lifetime is inversely proportional to the hole tunneling current, thin oxides are more robust at lower voltages.
One clever experiment provided further evidence against the hydrogen release mechanism. Jie Wu and his co-workers at the University of Illinois (Urbana-Champaign, IL) and Advanced Micro Devices (Sunnyvale, CA) knew that the lifetime of transistors was increased by a deuterium annealing step. If the hydrogen release model were correct, then performing that step with a hydrogen annealing step instead, thus replacing the Si:D bonds with Si:H bonds, would decrease the gate oxide reliability. No such effect was found, though, indicating that the hydrogen release model does not describe the mechanism.
MRS Part II: From practical processing solutions to future novel devices
Reports at the Spring Materials Research Society meeting in San Francisco ranged from developments immediately applicable for advanced processing to new measurement techniques, device structures, and R&D for potential future technology.
Very thin, uniform, conformal films, over wide areas and into deep trenches, is a need addressed by work on atomic-layer CVD. New measurement methods help to identify better diffusion barriers for preventing copper electromigration. Novel structures may help reduce short channel effects and parasitic resistance in CMOS devices. Laser-assisted processing keeps temperature down for making polysilicon transistors on plastic substrates and for making films for nanotechnology devices, such as quantum dots.
Suvi Haukka of ASM Microchemistry in Finland discussed atomic-layer chemical vapor deposition (ALCVD), which achieves large area, pinhole-free conformal films over large areas even with deep trenches. An excess of precursor molecules with a nitrogen carrier gas insures that all available reactive sites are filled (with covalent bonds), and then an inert gas (argon) purges the chamber before another layer is deposited. Dual damascene with low-k dielectric materials requires processing below 400°C, according to Haukka. Generally the reaction temperature is about 300°C and it takes about 3 sec to react. Oxides or nitrides can be grown on an HF-etched silicon surface, and the process also works on metallic surfaces, including copper. When asked about porous materials, Haukka replied, "We have ideas for this."
Work with ALCVD TiN barrier layer film deposition was reported by Alessandra Satta of IMEC in Belgium, collaborating with ASM Microchemistry. These titanium nitride films, deposited at 400°C and 350°C, showed clear superiority over ionized metal plasma (IMP) sputtered films, with a fine grain microstructure and lower surface roughness. The ultrathin films (10-30nm) showed high conformality on trenches and excellent thickness uniformity.
Use of a new transient-ion-drift (TID) technique for detection of low levels of copper, used in association with other measurements, demonstrated the superiority of a TaN barrier layer to Ta in recent studies. These studies were reported by Thomas Heiser, of Laboratoire PHASE-CNRS of the Univ. of Louis Pasteur, Strasbourg, France, in work done with others at STMicroelectronics, Crolles, and Royal Philips Electronics, Eindhoven, the Netherlands. TID allowed quantitative characterization of barrier efficiency, and in association with other analytical methods enabled the investigation of the relationship between barrier breakdown kinetics and film microstructure.
Elevated source drain (ESD) CMOS devices built using selective epitaxial growth (SEG) used shallow contacting junctions to minimize short channel effects and showed less parasitic series resistance than conventional devices, reported S.B. Samavedam of Motorola's Advanced Products R&D Lab, Austin, TX. The silicon ESD step can be inserted either before or after contacting S/D junction formation. The pre-clean sequence prior to SEG helps control facet formation at the silicon/spacer edge, loss of selectivity, and pattern loading effects. A modified RCA clean was used, eliminating a high temperature H2 pre-bake to minimize the thermal budget. The technique relaxes requirements on salicide scaling. The process has gone down to 100nm gate lengths, and the improved short channel performance will become increasingly important for sub-100nm devices. Work must still be done on further reducing the thermal budget.
As cobalt silicide is substituted for TiSi2 for saliciding, considerable study of cobalt migration and the spiking of CoSix was reported, including work to show how to optimize annealing temperature by Kenichi Goto of Fujitsu Labs.
Polysilicon transistors for flat-panel displays were widely discussed, including a report on making high-performance poly-Si TFTs directly on polyester substrates by Patrick Smith and co-workers at FlexICs, Mountain View, and Lawrence Livermore National Labs. Flash annealing with a 35 nsec excimer laser pulse keeps temperature at the plastic substrate below 250°C and even down to 100°C. After deposition, the whole device is coated with a doping layer and the laser flash melts it into the source and drain areas while an aluminum gate blocks doping of the gate channel. Partial laser exposure can smooth the rough surface. Some devices have achieved >250cm2/V-sec mobility in the top gate, n-channel, self-aligned TFTs.
Many other papers described laser-assisted deposition of thin films, including work at the U. of Florida, Dept. of Materials Science and Engineering, to lower substrate temperatures, reported by R.K. Singh. Lowering substrate temperatures below 650°C while retaining crystalline quality, stoichiometry and film properties requires a more reactive gaseous atmosphere. A second laser source during growth has shown promise, particularly for growth on sensitive substrates such as plastics, but this boosts costs. In this work, an inexpensive, low-pressure mercury lamp is used instead of the second laser, providing 185nm UV radiation to dissociate molecular oxygen. The Hg lamp is also used in the cooling phase.
Pulsed laser deposition (PLD) was used by a number of experimenters for ZnO, blue-emitting photoluminescence devices. For example, ZnO/MgZnO multiple quantum well superlattices were grown on sapphire at North Carolina State U. as reported by A.K. Sharma. UV lasers and solar-blind optical detectors are among the optoelectronic devices that might result from work like this.
A wide range of MRS presenters reported experimental work on nanotechnology, such as quantum dots, and potential device structures. Seung Jae Baik of the Korea Advanced Institute of Science and Technology described a silicon nanocrystal memory cell that might be used as a flash memory. A nanocrystalline silicon film was deposited by photo-CVD, and then oxidized in a dry oxygen atmosphere to obtain a 2-D Si nanocrystal array separated by SiO2. The nanocrystal layer served as a floating gate in a MOS memory device, an electrically erasable and programmable memory (EEPROM) structure. Each nanocrystal was 7nm, storing three electrons for a 2V threshold voltage shift. A negative differential resistance characteristic was observed with an increasing gate bias sweep.
An interesting aspect of the conference was the array of computers (both PCs and Macs) set up for Internet access by the attendees. There was almost always a line, sometimes a long one, even though users were urged not to spend more than 10 minutes on the Web.
IMEC implements single-damascene test structures
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At IMEC in Leuven, Belgium, insight into material properties — particularly with wafer-level porosimetry that details density, free volume, and interconnectivity of both porous and nonporous materials after deposition and after chemical and plasma processing — has allowed successful implementation of single-damascene test structures for full electrical characterization of the dielectric constants in narrow spacings. The relation between the material properties using real processing conditions and the electrical performance at critical dimensions provides valuable information in the debate between spin-on and CVD low-k dielectric choices. This SEM shows a single-damascene cross-section of a meander-fork structure with 0.2mm copper trenches and a porous spin-on low-k dielectric. (The bowing is an artifact of SEM imaging.)
Sub-100nm SOI CMOS with 248nm litho
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Existing equipment in combination with chromeless phase-shift masks and a double-exposure technique enabled Lincoln Labs to produce working sub-100nm silicon-on-insulator CMOS devices with a 0.6 NA 248nm stepper.
Details can be found in "Chromeless phase-shift masks used for sub-100nm SOI CMOS transistors," by Michael Fritze et al. on p. 116.
Sandia studies thin-film materials
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Sandia National Laboratories' (Albuquerque, NM) principal investigator Tammy Henson examines a new vacuum-deposited thin-film ultralight piezoelectric material that may find application in surveillance satellites and ultralight deployable (foldable for launch) mirrors in space telescopes. Initial work is being done with polyvinylidene fluoride, but for space applications piezoelectric polyimide thin-film materials look very promising. The film is "smart" because it changes shape when struck by electrons fired by a computer-controlled gun that is controlled via laser optical sensors measuring the shape of the mirror surface. Using electron gun excitation of piezoelectric materials is the brainchild of University of Kentucky researcher John Main. In a formal partnership, Henson is developing optical concepts and mirror-figure sensing systems, Main is pursuing research on the electron gun, and Sandia's Jim Redmond is developing precision shape-control algorithms for the piezoelectric mirror. Ultimately, the shape of this optical-imaging mirror can be controlled to within 10 millionths of an inch. This thin-film technology, still in its early stages, has already captured the interest of NASA officials and the remote-sensing community. (Photo by Randy Montoya)
IBM uses oxide layer for lower leakage, faster servers
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A cross-section of IBM's silicon-on-insulator (SOI) technology shows the islands of silicon in the oxide layer (see below). The oxide results in lower leakage compared to standard silicon substrates. This technology is now being used in a new line of IBM's AS/400e servers, the first appearance of SOI in production volume ICs. This product also uses copper interconnect, and the combination of SOI and copper helps the server perform 3.6 times faster than the previous generation. — J.D.