Asia Focus
07/01/2000
Japanese chipmakers lower costs with design/process integration, wafer-scale packaging
Add a new item to the litany of hot topics in any discussion of Japan's big chipmakers' strategy to regain market share. Now besides systems chips and process technology, it's integrated development.
Japan's big semiconductor makers count on regaining a competitive edge by integrating their process engineering and design. The vertically integrated manufacturers hope that by cultivating engineers who understand both production and design, and by developing an automated design environment that adjusts process recipe to circuit design and vice versa, they will have an advantage over foundries that do only production and design shops that do only design.
 Increasing integration of design and process engineering favors vertically integrated chipmakers. |
By working together, production and design should be able to make a better and cheaper chip than either can do alone. Taking a step beyond concurrent engineering, where design and process engineering exchange data, and beyond the virtual factory's computer simulations, the goal is to create a seamless development environment where automated process technology design is completely unified with automated circuit design (see figure on p. 67). Advances in technology CAD (TCAD) make this integration possible; the explosive growth of manufacturing prowess in Taiwan's fabs makes it vital. And the growing demand for systems chips that require top performance at low cost creates a market where this edge could make a significant difference.
To exploit this potential competitive advantage, Japan's big chipmakers are stepping up their TCAD development efforts. Integrating design and process engineering requires more sophisticated TCAD simulators to evaluate and apply the best process recipe to each part of the circuit pattern during the design process. So far companies have the simulators to integrate only some of the parts of process design into the circuit design. Toshiba Corp. is reputedly ahead of most other Japanese companies in TCAD usage, applying its TCAD simulations of lithography and circuit delay to the circuit design process to select the best exposure techniques and materials. It reports that such integration allows it to optimize the exposure process recipe for each separate pattern layer of the design; and to extend simple KrF exposure technology to 0.13mm, avoiding the need to switch over to more costly ArF processes (see Case Study 1).
Besides just better simulators, integrated development also demands process engineers who know something about circuit design, and designers who know something about process technology. Take for example the design of repeaters. Back when the effects of circuit delay weren't so significant, process engineers could just set the basic design parameters, and circuit designers could just put in as many repeaters as they needed. But now reducing circuit delay can be crucial, and putting in too many repeaters may make the chip too big. So the process engineer needs to know about the design of repeaters and their effect on chip size, know how many repeaters should optimally be used, and then adjust the process recipe to meet these needs.
So companies are restructuring their organizations to make process engineers and circuit designers work more closely together. NEC Corp., for example, has merged its process development group with its unit that develops the design environment. The company says integrating its process engineering and design, along with its TCAD simulators of circuit resistance and delay, has allowed it to optimize the thickness of copper interconnects for each individual circuit length, and reduce the number of repeaters, to significantly speed up performance and cut down chip size (see Case Study 2 starting on p. 64). — Yasuaki Nagahiro, Editor, Nikkei Microdevices
Wafer-scale packaging will become a low-cost alternative by 2003
Japan's pioneering suppliers of wafer-scale packaging say they'll get prices down to below those of conventional chip-sized packages (CSPs) by 2003 (see figure on p. 68).
The big appeal of wafer-scale packaging is, in theory, its potential to cut costs. But in practice, it hasn't been clear just how proponents of the radical new method of encapsulating chips before dicing them apart are going to actually produce these big savings. First suppliers found few takers, and ended up delaying their original plans to start commercial production by nine months to a year. But that may all be starting to change. Demand for CSPs of all types is growing fast, and producers of wafer-scale packages are touting specific strategies to bring down costs.
Major chipmakers plan to use some 1.3 billion CSPs of all types this year, 2.6 billion next year, and 5.5 billion in 2003, as they look for ways to make ever smaller and faster electronics gear, according to a recent survey by Nikkei Microdevices. And they expect to use wafer-scale packaging for a third of these CSPs by 2002. Spurring this enthusiasm for all sorts of CSPs, but especially for the even smaller wafer-scale packages, is a cheaper fine-line circuit board to mount them on, as Intel's volume use of buildup board substrates for its microprocessor packages brings down costs at last.
 Roadmap for lower wafer-scale package prices. |
While switching from a traditional QFP to a CSP can drastically reduce the unit's size by 75-90%, going to wafer-scale processing trims it only another 20% or so. So unless wafer-scale package prices are dramatically reduced, no one will make the change, notes Junichi Kasai, assistant GM of Fujitsu's LSI package development group, which developed wafer-level CSPs.
Shinko Electric Industries Co. Ltd. now figures it can make wafer-level packages for about a third less than regular CSPs, primarily by cutting material and tooling costs, but also trimming initial testing, labor, and other costs. "It's possible we can get costs down below 0.2 yen/pin [essentially equivalent to 0.2 cents/pin at current exchange rates of x106/$1] by late 2002 or 2003," says Mitsuharu Shimizu, manager of Shinko's advanced package development department. The company started wafer-scale packaging of flash memory in February. Current costs range around 1.5-3.0 cents/pin.
Also ramping up production is Oki Electric Industry Co. Ltd., which started wafer-scale packaging of low-power logic in March. Oki is using technology developed by IEP Technologies, its joint development venture with Casio Computer Co. Ltd. "We'll be able to reduce costs in stages, from 0.6 yen [or cents]/pin in 2001, to 0.4 yen/pin in 2002, to 0.25 yen/pin in 2003," says Harufumi Kobayashi, IEP's VP of marketing.
These producers expect to realize the biggest savings from reducing the cost of materials and tooling. They're now spin coating on liquid photoresists and insulating layers, which wastes up to 80% of the material. But they're working on converting to dry film resist and then dry insulating film, which they figure will cut waste down to 10%, dramatically cutting materials costs.
Both Shinko and IEP get further savings from eliminating initial testing. Since they start by covering the wafer surface with a barrier metal that prevents damage from static electricity, there's no need for the usual first testing process.
Automation should also bring down costs. Producers of conventional CSPs can't automate production very well because each kind of chip is a different size. But wafer-scale packaging processes are all done on the same-sized wafer for all kinds and sizes of chips, so it can conveniently be fully automated. Neither Shinko nor IEP has yet done so, but both say they plan to automate once production volume increases. IEP says it will automate production once it gets up to running 5000 wafers/month. Shinko is still making too many different trial products on its line to automate, but says it has now settled on the three most promising types to move toward more efficient production.
It will make Fujitsu's Super CSP, Form Factor's MOST type, and its own re-route-type package.
Finally, the wafer-scale package suppliers expect to reduce spending on equipment, since they use fairly simple, standard semiconductor-manufacturing processes. Initially, they even thought they could get by with older-generation second-hand equipment, but that hasn't worked out as hoped. IEP did use some used equipment for development, but found it couldn't keep up the necessary throughput. Now both companies are working with equipment suppliers to develop low-cost tools without any unneeded sophisticated capabilities. — Masahide Kimura
Case Study 1: Toshiba and Fujitsu adjust process recipe for each circuit pattern
Toshiba Corp. and Fujitsu Ltd. have extended simple KrF excimer laser technology to 0.13mm DRAM patterns, eliminating the need for either enhanced exposure processes or an ArF excimer laser light source, potentially reducing costs by as much as 43%.
Essentially, the joint research group used computer-aided design of exposure technology in the circuit design process to determine the best individual process recipe for each separate pattern layer. While process engineers have used TCAD for the last several years to figure out how to handle shorter wavelengths, higher lens apertures, and vexing optical proximity effects to get the best resolution, from now on they'll have to consider the circuit design as well to get the best results.
By adjusting the process recipes to the design, we made 0.13mm lines without Levenson phase-shift masks or other enhanced exposure techniques, saving about 12% in cost. Avoiding ArF lithography equipment, masks, and resists reduced costs by as much as 43%. Concurrent design and process development also cut time to production.
First, we analyzed the production process to set design parameters. We looked at all the causes of variation and at how precisely we could control them to figure out the depth of focus and latitude of exposure dose we needed to be able to manufacture 0.13mm devices. We improved the lithography equipment to reduce the variation in the depth of focus so we could maintain it at 0.4mm. And we made the mask pattern more precise to control the variability in exposure dosage for an exposure latitude of 9%. So we knew we could manufacture a 0.13mm device with 0.4mm depth of focus if we could get an exposure latitude of 9%.
Then, for each different circuit pattern we got from the designers, we used TCAD to find the simplest specific process recipe that would give this 9% exposure latitude. We were able to make all the patterns with a KrF source using some combination of half-tone masks, negative resist, and quadrupole exposure, and then applied optical proximity correction (OPC) only where needed. We used half-tone masks on all patterns, and negative resist to increase exposure latitude on the barrier and plug layers. The capacitor layers also required quadrupole exposure.
Then we applied model-based OPC to those areas still requiring better exposure latitude. The OPC tool checked the pattern layout against its rule table to see if it had an existing correction to apply, or, if not, it ran a simulation-based correction engine to calculate the best correction, which it then added to the rule table for future use. A typical 25mm2 mask can be corrected in about four hours, although the time depends on the amount of mask data. — Soichi Inoue, ULSI Process Engineering Laboratory, Microelectronics Engineering Laboratory, Toshiba Semiconductor Co.
Case Study 2: NEC adjusts design process to reduce delay of copper interconnects
NEC has developed a "triple damascene" interconnect technology that combines dual damascene copper interconnects of different depths on the same layer. The approach can reduce delay on the critical path by as much as 25% without adding extra process steps or increasing the size of the chip.
This improved performance comes from process engineers and circuit designers working together and integrating capacitance and delay simulation tools into the circuit design process. The designers can then include process technology information in the mask data they send to production. And production can adjust its process recipes for trench etching and metal implantation to best suit the design data.
 Figure 1. Optimal interconnect thickness depends on length. (Source: NEC) |
Such integration of design and process technology will become increasingly important in the development of next-generation semiconductors. Beyond 0.25mm, the increasing capacitance and resistance of the very fine lines cause significant delay. While process engineers try to speed up performance with new materials like copper interconnects and low dielectric insulators, designers focus on design solutions such as inserting repeaters. But both these separate approaches have their limits, and further progress in improving chip-level performance is likely to come from better integration of design and process engineering.
By integrating process engineering with design, NEC can adjust the resistance of the interconnect as needed in the design to reduce delay. And we increase the resistance by making the interconnect deeper instead of wider, so it doesn't take up any more of the chip's surface area. We make both deep and shallow trenches in the same layer, so they don't require any extra process steps. The process is called triple damascene because the deep trenches, shallow trenches, and via holes are all made at the same time.
 Figure 2. Triple damascene technology. (Source: NEC) |
Along with their usual CAD tools, the designers use new TCAD tools that simulate capacitance and delay, allowing them to adjust the thickness of each interconnect according to its length for best performance. When the circuit is short, a thinner line has shorter delay time because it has lower capacitance. But when the circuit is long, a thicker line has shorter delay time, because it has lower resistance. Finding the optimum thickness for a 10mm interconnect can reduce delay by as much as 25%. And making the interconnects thicker by making them deeper instead of wider can mean eliminating two of ten repeaters on a 20mm circuit, reducing the size of the typical 0.13-0.18mm chip by about 5% (Fig. 1). After roughing in the design, the designers calculate the delay time on the critical paths and the size of the chip, and then adjust the depth of the interconnects where needed to reduce both circuit delay and chip size. The mask data they send to production includes these parameters for etching trenches of different depths in different places.
 Figure 3. New circuit structure reduces repeaters. |
Key to producing both deep and shallow trenches in the same layer is a plasma SiN stopper film, topped with SiO2 insulator, that's put under the shallow trenches to prevent them from being etched as deeply as the deep trenches and the via holes. These shallow interconnects connect to the layer below through regular via holes, while the deep circuits open all the way through to connect directly. A deep circuit that isn't supposed to connect with the layer below is made shallower where necessary to form a bridge over the circuit underneath. The deep trenches are made with the same mask as the via holes, and are etched and implanted at the same time as either the vias or the shallow trenches, so the new process requires no additional masks or process steps (Figs. 2, 3).
NEC's test device had 0.28mm lines and 0.28mm spaces, with interconnects both 0.3mm and 1mm deep. — Noriaki Oda, ULSI Device Development Division, NEC Electron Devices
*These articles were translated for SST from the April 2000 issue of Nikkei Microdevices.