Chromeless phase-shift masks used for sub-100nm SOI CMOS transistors

07/01/2000

Michael Fritze, David K. Astolfi, Donna-Ruth W. Yost, Peter W. Wyatt, MIT Lincoln Laboratory, Lexington, Massachusetts*
Hua-Yu Liu, Numerical Technologies, San Jose, California
*Additional authors are listed in the Acknowledgments

Figure 1. Isolated phase-edge sensitivity to coma, showing that chromeless provides the best case.Click here to enlarge image

The application of chromeless phase-shift masks to sub-100nm gate length SOI transistor fabrication has achieved considerably enhanced resolution performance compared with alternating aperture while still preserving good process latitudes. The maskmaking process uses a simple, single-step dry etch with no minimum geometry features, thus simplifying mask fabrication. In wafer fabrication, using just a 0.6 NA 248nm lithography tool and commercially available resists and antireflection layers, researchers achieved lithography results for k1 factors down to 0.10 for isolated features and 0.3 for dense features. This corresponds to 40nm (isolated) and 125nm (dense) CDs on the stepper, or l/6 and l/2 resolutions, respectively. Excellent pattern transfer into polysilicon was achieved using a high-density plasma etch process producing gate features down to 25nm linewidths (k1 = 0.06, or l/10 resolution). The net results were sub-100nm gate-length fully depleted SOI CMOS transistors with excellent short-channel behavior down to 50nm physical gate lengths.

Figure 2. a) 55nm CD isolated gate resist features over 60nm topography and b) a cross section of a 50nm gate with an aspect ratio of 5.5:1.Click here to enlarge image

Currently, 180nm design-rule devices are being produced using 248nm wavelength lithography tools, with further shrinks to 150nm and 130nm on the industry's near-term roadmap. These lithography requirements have increased the interest in resolution enhancement techniques to obtain good resolution and process latitude at ever-decreasing k1 factors. Strong phase-shift methods, such as alternating aperture and chromeless, offer the largest potential resolution increase if they can be incorporated into a practical process module. The ultimate practical limit of these methods has yet to be determined.

With this backdrop, we set out to look at the application of chromeless phase-shift masks to sub-100nm-gate-length fully depleted silicon on insulator (FDSOI) CMOS transistor fabrication [1]. Our principal lithography effort was the extension of Numerical Technologies' double-exposure technique to chromeless PSMs [2]. Two masks are used in this method. The first is a darkfield mask with chromeless edges defining the minimum geometry gates, and the second is a binary trim mask that patterns larger gate features. This approach provides considerably enhanced resolution performance compared with the alternating aperture method, while still preserving good process latitudes. Our goal was to fabricate next-generation transistors using currently available DUV tools and resists by performing gate-only scaling of Lincoln Laboratory's existing 0.25mm SOI CMOS process [3].

Some background

Figure 3. Smile plot for phase-edge gate features.Click here to enlarge image

Chromeless phase shifting was first proposed a number of years ago [4] and was found to possess superior resolution and depth-of-focus (DOF) performance with respect to other "strong" PSM methods. It has since found only limited acceptance in actual device fabrication. There have been many unresolved issues regarding layout complexity, CD control, mask fabrication, aberration sensitivity, and mask inspection. There has been much recent progress in these areas, however, making the chromeless approach viable for actual device fabrication [5].

Commercial simulation, layout, and verification tools now exist. PSM mask fabrication also has made progress. Although a particular concern is the sensitivity of strong PSM approaches to lens aberrations [6], recent results [7] show encouraging behavior. Another area of major concern is image-shifting coma effects [8].

We carried out a PROLITH simulation of effects of 0.1 wave of coma on the position shift of an isolated line imaged by a chromeless phase edge. We found that the image shift depends only weakly on chrome regulator width, actually decreasing as the regulator width approaches zero (Fig. 1). Image shifts in the 40nm range are not significant for a partially scaled application, but they can become a major issue for more fully scaled applications of strong PSM.

Metrology and mask inspection also remain major challenges, but progress also is being made in these areas.

Experimentation

Figure 4. CD versus dose at best focus for phase-edge gates. Click here to enlarge image

For our work, layout conversion of a 0.25mm-design-rule multi-project test chip was performed by Numerical Technologies using its iN-Phase software. We used a chrome regulator width of zero for the phase-edge features to implement chromeless edges. All 0.25mm transistor gates were converted to chromeless phase-edge features.

Our device masks were fabricated at the Photronics advanced mask facility in Milpitas, CA. Technologists there used a single-trench dry etch process for the phase edges with no wet undercut. The two masks used in the double-exposure process have no minimum-width CD features, further simplifying the mask fabrication process. This fact, together with the high-contrast aerial image provided by chromeless phase edges, is expected to minimize the mask error enhancement factor (MEEF) [9-11], another key advantage of this method.

We developed an aggressive high-density plasma etch process to transfer these small phase-shift gate patterns into polysilicon on thin gate oxides. This used a LAM TCP 9400 high-density etch tool employing Cl2-HBr chemistry. The resulting three-step process consisted of an antireflectant coating (ARC) etch, main polysilicon etch, and overetch, the first two optically endpointed. We achieved good selectivity to our 4nm-thick gate oxide.

Isolated features

Figure 5. Etched a) 50nm polysilicon gate features and b) 60nm polysilicon features. The "residue" in Figure 5a is due to an incomplete LOCOS strip process.Click here to enlarge image

We used our Canon EX-4, 0.6NA, 248nm exposure tool with partial coherence of 0.3 for the phase-edge exposure and 0.65 for the chrome exposure. Our resist was Shipley UV-5 positive resist with thicknesses in the range of 255-325nm on AR-3 ARC in the 62-100nm-thickness range.

A top-down SEM of the dark field chromeless phase-shift (DFCPS) method applied to one of our circuits shows well-defined 55nm isolated gate-resist features, corresponding to k1 = 0.13, over 60nm of SOI island topography (Fig. 2a); we did not observe necking effects at the island edges. A representative cross section through these gate structures shows a 50nm gate with an aspect ratio of 5.5:1 (Fig. 2b).

Note the smooth resist sidewalls and nearly vertical profiles achieved. Figure 2b shows some profile narrowing near the resist-ARC interface. This profile caused pattern-collapse problems for gate feature sizes in the 50nm regime. We traced this problem to a chemical interaction between the resist and photoacid present in the ARC resulting in an "antifooting" profile. We solved this problem, and the associated pattern collapse, by increasing the ARC bake temperature, thus more efficiently driving off the photoacid responsible for this effect.

Figure 6. Tilted SEM image of 25nm polysilicon gate on a locally thinned silicon channel.Click here to enlarge image

When we generated a smile plot for the phase-edge gate features from this data, we observed that DOF was quite large for sub-100nm feature sizes, retaining a remarkable value of 0.6mm at 40nm feature size (Fig. 3). More complete full-field DOF measurements are underway to more fully characterize this process. Figure 4 shows a plot of the CD versus dose, at best focus, for phase-edge gates. We performed a power law fit for this curve, yielding constant exposure latitude of 7.3%. Robust manufacturing processes typically have 10% exposure latitudes, so some improvement might be needed for widespread application.

Top-down SEMs of 50nm polysilicon gate features transferred using the Cl2-HBr etch process (Fig. 5a) and a cross section of 60nm polysilicon features (Fig. 5b) show the excellent sidewall profiles achieved at the small gate length.

Figure 7. SEM cross sections of 250nm pitch resist gratings showing 110nm lines and 140nm spaces.Click here to enlarge image

We used a 15nm etch bias to transfer gate features as small as 25nm into polysilicon (Fig. 6), thus fabricating features near the expected physical limits of CMOS functionality using currently available DUV imaging and high-density plasma etch processes. The same DFCPS method can be applied with a negative resist to fabricate sub-100nm slots for damascene gate applications.

This part of our work showed that we could achieve good isolated line lithography down to k1 = 0.10, corresponding to 40nm CDs for our DUV exposure tool, or l/6 resolution. We achieved good process latitudes with DOF of 0.6mm at feature sizes as small as 40nm. The exposure latitude of 7.3% might be an issue for a robust manufacturing process, however, and more study of full-field CD control is required. These results allow aggressive, next-generation transistor devices to be developed using currently available DUV optical lithography.

Dense features

Although not immediately required by our device fabrication needs, we also explored the imaging and pattern transfer of dense grating features with the DFCPS method.

Figure 8. SEM cross section of 250nm pitch grating imaged with DFCPS and transferred into polysilicon.Click here to enlarge image

We used Shipley UV-6 resist on AR-3 antireflectant due to its superior dense feature performance. Our results show that a feature pitch approximately equal to the 248nm-exposure wavelength can be resolved. This corresponds to a k1 = 0.3 for nearly equal lines and spaces — 110nm lines and 140nm spaces (Fig. 7). This is quite close to the physical Rayleigh limit of k1 = 0.25 for dense features. Here, the DOF is ~1mm, with a 10% exposure latitude for these features.

Patterns were transferred into polysilicon with CDs down to 36nm, stopping on the 4nm-gate oxide (Fig. 8). Here, with an aspect ratio of 5.5:1, the sidewalls are excellent and nearly vertical. These feature sizes are once again approaching the expected physical limits of CMOS functionality and were fabricated by currently available DUV tools. Line-edge roughness effects visible in Fig. 8 are becoming important at these small feature sizes, and their origin and effect on device performance require further study [12].

Click here to enlarge image

The control of optical proximity effects is an important challenge faced in applying strong PSM methods to dense features and must be dealt with by some type of optimized OPC correction [13, 14]. Such proximity effects remain a major concern, but they play only a minor role in our application because the semi-isolated gates we are fabricating are spaced by at least 0.45mm, typically more.

We have also investigated evidence for mask topography effects in the dense gratings that we fabricated. Three-dimensional (3D) mask topography effects are expected to produce diffraction asymmetries between etched and unetched mask material, giving rise to linewidth and pitch asymmetries in the images [15-17]. Figure 9 shows 250nm pitch grating structures at two different exposure doses; compare the clear pitch asymmetry present at a low dose with the symmetric pitch obtained at a higher dose. The graph in Fig. 9 summarizes the data, showing that no pitch asymmetry is present for spacewidth greater than or equal to linewidth. No left-right linewidth asymmetry was observed in the dense grating features. Image asymmetries due to 3D mask topography effects play only a minor role in a partially scaled device process where the gate features are semi-isolated.

Application to transistor fabrication

The control of short channel effects is critical in the design of transistors with aggressively scaled gate lengths [18, 19]. Fully depleted SOI technology has important advantages in this area because junction depths can readily be kept shallow. In addition, we have used a LOCOS process to locally thin the channel region below the gates [20, 21]. The thinning of the silicon in the transistor channel region is the key to controlling short channel effects and permits reasonable sub-100nm gate-length devices to be implemented with a single-gate approach. The thinned channel region also allows a simpler implant process to perform the required channel engineering.

On our "THINFET" SOI transistor device (Fig. 10), the SOI thickness in the source-drain regions is typically around 60nm, and the channel is locally thinned under the gate region to around 20nm. Dual-doped polysilicon gates are used with thin silicon nitride spacers and a 4nm-gate oxide. The source, drain, and gate receive a cobalt silicide treatment to lower resistance.

To speed up fabrication time and enable us to properly tune the transistor channel engineering, our first lot was made up of NFET and PFET devices on separate wafers. We performed a three-way split targeting 85nm, 50nm, and 25nm polysilicon gate lengths. The lot yielded functional NFET and PFET devices for 85nm and 50nm physical gate lengths. These preliminary results were quite encouraging in terms of current drive, off current, and subthreshold slope. The threshold voltage for the PFET devices was below the desired -0.3V target, and we plan to adjust this in subsequent lots by modified channel engineering.

Conclusion

Figure 10. "THINFET" SOI transistor device schematic.Click here to enlarge image

We have achieved lithography results using DFCPS imaging that show excellent resolution and process latitude down to k1 = 0.10 for isolated gates and k1 = 0.3 for dense gratings. This corresponds to 40nm (l/6) and 125nm (l/2) feature sizes, respectively, on our 0.6 NA, 248nm stepper. Further, we saw excellent pattern transfer into polysilicon for gate feature sizes down to 25nm (k1 = 0.06, or l/10 resolution) near the expected physical limits of CMOS functionality.

We have applied the DFCPS imaging method to the fabrication of highly scaled SOI CMOS transistors. Good performance characteristics were achieved for PFET and NFET devices down to 50nm physical gate lengths. Thus, we have been able to perform next-generation transistor technology development using currently available DUV optical lithography.

All the benefits of DFCPS imaging should also be realized with 193nm or 157nm exposure sources, which also would permit more aggressive feature pitch scaling, thus providing a clear evolutionary path for future lithography development. Dense grating features of 67nm lines and spaces should be possible by extrapolating our DUV results to a 0.75NA, 157nm exposure tool, which is expected at Lincoln Laboratory later this year.

Acknowledgments

Additional authors are Tony Forte, Paul Davis, Andrew Curtis, Doug Preble, Sue Cann, Sandy Denault, MIT Lincoln Laboratory; Joseph Shaw, Photronics, Milpitas, CA; and Neal Sullivan, Robert Brandom, Marty Mastovich, Schlumberger ATE, Concord, MA.

References

1. The Lincoln Lab portion of this work was sponsored by the Defense Advanced Research Projects Agency under Air Force Contract #F19628-95-C-0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the US government.
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Michael Fritze received his MS and PhD in physics from Brown University. With principal responsibilities in advanced lithography development and SOI transistor engineering, Fritze is a staff member at MIT Lincoln Laboratory, 244 Wood St., Lexington, MA 02420; ph 781/981-2626, fax 781/981-7889, e-mail [email protected].

David K. Astolfi received his BS in plant and soil science from the University of Massachusetts, Amherst. Astolfi is the supervisor of the advanced lithography area of MIT Lincoln Laboratory's Microelectronics Lab.

Donna-Ruth W. Yost received her BS in materials science and engineering from Cornell University. Yost is a staff member in the Advanced Silicon Technology Group at MIT Lincoln Laboratory, responsible for plasma etch and deposition and the integration of these processes with fully depleted SOI CMOS circuits.

Peter W. Wyatt received his BS from Caltech and PhD from Yale. After several years at Bell Laboratories, he has been at MIT Lincoln Laboratory since 1977. Wyatt is associate leader of the Advanced Silicon Technology Group at MIT Lincoln Laboratory, with particular interest in SOI devices and ultra-short-channel MOSFETs.

Hua-Yu Liu received her MS in chemistry from California State University. She worked on electron-beam technology and optical enhancement techniques at Hewlett-Packard Research Laboratories for 14 years. Liu is a senior director of technical marketing at Numerical Technologies.