TCAD physical verification for reticle enhancement techniques
07/01/2000
Mike Rieger, John Stirniman, Avant! Corp., Fremont, California
overview
The industry's accelerating use of reticle enhancement technologies—optical proximity correction and phase shift masking—has brought along with it a need for automatic verification of photomask images, which are no longer exact replicas of the circuit design layout. Fortunately, this need can be adequately met using TCAD software solutions that provide built-in design rule checking alongside model-based lithography checking. In the end, today's most advanced mask layouts can be verified for enhancement structure synthesis accuracy, structural integrity, and conformance to mask fabrication rules in one pass.
Widespread adoption of reticle enhancement technologies (RET) has drastically complicated physical verification. Gone are the days when the photomask layout is an exact replica of the design layout, and where the mask image is faithfully transferred to the wafer. In today's deep submicron lithography regime, the original design, the mask layout, and the structures printed on the wafer bear little resemblance to each other (Fig. 1). The growing array of RETs moves photomasks from their former role as mere master images of the chip to complex optical instruments in their own right. RET synthesis methods, such as optical proximity correction (OPC), phase-shift mask (PSM) generation, assist features, and dummy fill, are now used, often in combination, to produce photomask layouts many times more intricate than the original design layout.
The key verification challenge is to confirm that RET treatments on the photomask layout will accurately produce the desired result on the wafer, and to make sure that nothing else is defective in the mask layout synthesis process. High-speed technology computer-aided design (TCAD) simulation not only meets this verification challenge, but it also provides an extraordinarily clean, one-pass solution.
Verifying OPC
At process geometries of £0.25µm, nearly all leading semiconductor manufacturers are using some form of OPC. Optical and process proximity effects cause significant distortions in the configurations transferred from the mask to the wafer. With feature linewidths near the lithography wavelength, proximity-induced effects cause linewidth variations of approximately ±10% of the critical dimension (CD), thus using up most or all of a typical CD error budget. Proximity distortions escalate rapidly as feature dimensions drop below lithography wavelengths to the point where features not only change shape, but also can disappear altogether without OPC.
Some chip manufacturers use ad-hoc OPC methods based on design rule check (DRC) tools. Alternatively, for advanced DRAM, microprocessor, DSP, and ASIC production, these manufacturers are increasingly using commercial model-based tools, such as Avant!'s Taurus-OPC. *** Typical OPC treatments involve biasing features on the mask layout to compensate for systematic shape distortions in the pattern-transfer process. Systematic distortions include combined characteristics of the maskmaking tool, mask process, wafer exposure tool, and wafer layer development process. Two current methods for calculating OPC are the so-called "model-based" and "rule-based" approaches.
In model-based methods, a chip pattern undergoes TCAD simulation to obtain predicted wafer shapes. Differences between predicted shapes and the desired shapes are used to calculate the biases needed along feature edges to compensate for the deviations. Typically this is an iterative process because a shape change on one feature influences corrections needed on neighboring features.
Rule-base approaches have evolved from DRC synthesis methods, where OPC biases are predetermined in tables based on linewidths and spacings associated with each feature edge. Table values are usually interpolated from empirical measurements taken from a test wafer.
Regardless of the OPC method used, the key OPC verification goal is to confirm accuracy of the correction by ensuring the correction shapes defined on the mask layout achieve the desired result on silicon. Other goals include verifying structural integrity of the OPC pattern and ensuring the mask layout conforms to layout constraints imposed by mask fabrication and inspection.
Standard design-rule checking procedures are used to check for minimum spacing, widths, and jog sizes based on mask writing and inspection design rules. (These rules are different from chip design rules used in ECAD physical synthesis.) Structural checking can be achieved with DRC methods by comparing the OPC pattern with the original layout. Differences are the correction figures, which are known to be relatively small, compared to feature sizes. Any difference larger than the maximum expected correction suggests a missing or misplaced figure, and it is flagged as an error. Traditional DRC methods, however, give no clue to the accuracy of the corrections.
The most robust way to verify accuracy is to apply TCAD simulation to the full-chip mask layout. The concept is simple in theory: simulate the entire chip layout to predict the shapes of all features on silicon, then compare the predicted layout to a reference pattern defining the intended wafer configuration (the ECAD layout, to first order). The biggest hurdle for production-worthy implementation is speed of simulation on large layouts. An extremely fast simulation method is needed to deal with the huge amount of layout data in DSM designs. Our behavior modeling technology, for example, can simulate layouts several orders of magnitude faster than traditional TCAD technology (See "Behavior modeling compared to physical simulation").
Our lithography rule checker (LRC [1]) integrates proven DRC technology with behavioral modeling technology and proximity-aware hierarchic data-handling methods to provide one-stop verification. This TCAD tool verifies full-chip OPC accuracy by comparing predicted wafer configurations from the mask layout with the design intent layout. Built-in DRC capability is applied to verify structural integrity and conformance to mask fab design constraints.
A key issue for OPC verification is to define the design intent precisely. Because it is not practical to create perfect corrections in light of mask and data-volume constraints, the reference comparison must be tempered with realistic tolerance values. Furthermore, the tolerances should be applied in a feature-specific way; for example, gate regions typically need the tightest tolerances, whereas more latitude is allowed for interconnect features.
Another issue is that the original design layout does not exactly represent the intended wafer configuration. For example, corner rounding, an unavoidable consequence of wafer lithography, is ignored in the original design where all figures have perfectly square corners.
 Figure 2. LRC violation "channel" check figures. |
Further complicating reference pattern definition are locations where proximity corrections are present in the original design. A common example is extending line ends in the original design to compensate for line-end shortening expected in lithography. The true intent of the line-end position is somewhat shorter than the design-drawn location.
The approach we adopted is to provide user-defined filtering of the original design layout to generate a reference pattern for comparing to the simulated wafer image. Feature-dependent control of corner rounding, line-end adjustments, and tolerance limits are provided to produce a reference check configuration (Fig. 2). The LRC operation checks to ensure that the expected feature edges fall within the boundaries of the "channel check" figures. Locations of violations, if any, are recorded in an error file, and violation flag figures are placed in an output layout file.
Verifying alternating PSM
After nearly 20 years since its invention, strong PSM technology is now slated for production at leading chip suppliers. Alternating PSM lithography leverages interference effects created by modulating phase angles of light transmitted through the photomask to produce wafer linewidths smaller than those possible with conventional lithography (Fig. 3). By making the light rays on either side of a critical feature 180° out of phase with each other, constructive interference forces the intensity to make a sharp transition to black. In addition to yielding smaller features, PSM provides significantly better CD control through depth of focus than conventional lithography.
Current industry focus on strong PSM is to apply it selectively on gate structures in the polysilicon layer. The goal is a chip of conventional scale but with faster transistors created with PSM-shortened gate lengths. Typically, the lithography step for a single wafer level involves two exposures with two masks (Fig. 4).
A PSM exposes regions on either side of each gate to create a thin line of unexposed resist. A second exposure with a conventional mask exposes the polysilicon interconnection features at conventional scale and feature sizes.
The resist is developed after both exposures are made. Extended applications of strong PSM to enhance interconnect density are on the horizon.
 Figure 3. PSMs straddle critical features with 180° phase shifts on either side. |
An automated PSM synthesis tool uses the original polysilicon and active diffusion layout patterns to generate three layers defining the mask set. Two layers define the alternating regions for the PSM, and the third layer defines the trim mask. Conforming the synthesized mask structures to wafer lithography and mask constraints is extraordinarily complex. Phase-region placements must be checked to ensure that phase interference occurs where needed, and that it does not occur where it can be harmful. Conformance to both conventional and PSM fabrication constraints must also be assured. Our PSM synthesis software [2] employs extensive built-in checking capability to ensure that all geometric constraints are correct by construction.
Another problem today is that existing layout designs have been made without consideration for phase-shift constraints on relative feature placements. Configurations can occur where no phase-map solution is possible. An example is a cyclic conflict where phase regions cannot be arranged so that every critical feature is
straddled by opposite phases. Therefore, the first objective of PSM verification is to ensure that the original design is PSM-compliant. If errors are present, the TCAD software must provide a complete report on all conflicts arising from design configuration.
PSM synthesis is not complete until OPC is performed. Although PSM layer generation defines the locations of phase and trim figures, OPC is required to achieve accurate dimensions of the printed features. PSM-OPC is complicated by the need to correct three masking layers together, taking into account all interactions and constraints among them. Model-based OPC, such as that provided by our software with its underlying multiple-layer behavior modeling, effectively handles trim and phase mask interactions by correcting all three layers simultaneously.
Our software can be used post-OPC to verify the combined PSM and OPC behavior of mask layout. The lithography model operates on all three layers to simultaneously simulate the combined effect of the PSM and trim mask exposures. The reference pattern is solely focused on defining the structures needed on the wafer, and its construction from the original layout involves the same treatments used for verifying conventional OPC discussed earlier.
Verifying attenuated PSM
 Figure 4. Double-exposure selective PSM procedure. |
Today, attenuated (or halftone) weak PSM is widely used for dark-field contact masks. Instead of conventional opaque and clear areas, attenuated phase masks use clear and partially transmitting regions with opposite phase shifts. OPC for attenuated PSM configurations is similar to OPC for conventional masks in that only one layer is treated at a time. A side effect of attenuated PSM is that sidelobes in the projected light from the main features leak through the partially transmitting chrome. Normally, an isolated sidelobe will not have enough energy to expose the resist. Certain configurations of feature placements, however, can focus sidelobes in locations where they reinforce each other and expose an unwanted figure in the resist. Lithography verification for attenuated phase-masks should include a check for such spurious features. In addition to "channel checks," our software provides another check feature, the "trespass check," which tests whether the exposure intensity anywhere within the check feature is sufficient to cause the resist to be exposed. Geometric computations are used to determine anywhere a sidelobe problem might occur. Then those places are tested with simulation to determine if a problem actually occurs.
Verifying assist and dummy features
RETs include a class of treatments where additional features are added to the mask layout. Subresolution assist features are strategically placed on the mask to enhance the depth-of-focus performance of optical projection systems. In most cases, assist feature dimensions are sufficiently small so that they do not themselves get printed on the wafer.
Because assist features are placed well within the range of proximity effects, they must be included in OPC computations. Typically, the optimum placement for assist features is computed with geometric rules, and then OPC is performed on the main features, taking into account the influence of the assist features.
 Figure 5. Physical synthesis flow with lithography verfication. |
A couple of things can go wrong with assist feature synthesis. First, the assist features might interact with main features in a way that lowers contrast and makes the layout vulnerable to bridging. Second, assist feature interactions can cause them to inadvertently print on the wafer. Both of these potential problems can be identified with TCAD channel and trespass checks.
Dummy features are placed in large, open spaces on the mask layout to help level the feature density across the layout. Uniform feature density improves wafer-processing uniformity for certain operations such as chemical mechanical polishing (CMP). Usually, dummy features are placed far enough from critical features to ensure they do not induce optical proximity effects. Long-range effects, such as those encountered in reactive ion etching, can influence pattern fidelity, however. LRC verification, using a long-range behavior model, should be applied (to the main circuit features), taking into account the influence of dummy features. Unlike assist features, dummy features are transferred to structures printed on the wafer. Also, it is important to verify that they do not contribute inadvertent electrical interactions with the circuit. This kind of check is best performed with conventional DRC methods.
Lithography compliance in design
RETs place new constraints on ECAD design. Some design configurations, such as PSM cyclic conflicts, can present fundamental barriers to RET application. Similar problems occur in OPC where certain configurations cannot be optimized for a particular set of model conditions or fabrication constraints. In either case, the only solution is to modify the original design configuration. Today, many of these problems are not discovered until PSM and OPC are applied. Much time and expense are lost backtracking through the design process to modify the layout.
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New methods are needed to ensure that RET-unfriendly configurations are prevented as early as possible in the design flow. Some RET constraints can be encompassed within traditional design-rule constraints, but others involve complex, multiple-feature interactions difficult to codify within the framework of space-width-based design rules. Cyclic PSM conflicts, for example, can involve conflict loops through an unlimited number of features. A robust way to completely identify all such layout problems early is to periodically apply RET and lithography verification at various physical design steps, including library design, place and route, and full custom layout. Because lithography compliance parameters will be foundry-specific, checks for all intended fab sites should be made.
Often, chip designs must be well underway, before the target wafer process is available and empirically characterized. In these situations, TCAD process simulation tools [3] can provide early SPICE parameters, optimal layout design, accurate interconnect models, yield optimization, and early libraries to designers before running first silicon. This enables IC manufacturers to shorten the design cycle and produce high-performance products with high yields. This approach also can be used to provide behavior models of the anticipated process to support lithography compliance in leading-edge chip design.
Conclusion
TCAD-simulation techniques provide robust verification for all RET mask layout treatments. When the TCAD platform provides built-in DRC checking alongside model-based lithography checking (Fig. 5), the mask layout is verified for RET synthesis accuracy, structural integrity, and conformance to mask fabrication rules in one pass (see Table 1). Advanced design methodologies will include TCAD-based verification to ensure that layout designs are optimized to target process characteristics, and that they conform to constraints dictated by RET synthesis methods.
Notes
- Commercially available as Taurus/Mask-LRC.
- Commercially available as Taurus/Mask-SPSM.
- Such as Avant!'s Silicon Early Access (SEA) tool suite.
Mike Rieger received his AB/BE from Dartmouth College and his MSEE from Stanford. Prior experience includes applied research management at Tektronix Laboratories, and marketing and engineering management for Ateq Corp. He also was a technical director for ETEC. Rieger co-founded Precim Corp. in 1993, which was merged in 1997 with TMA and Avant! He is currently an engineering manager at Avant! Corp., 9205 S. W. Gemini Dr., Beaverton, OR 97008; ph. 503/520-4360, fax 503/520-4368, e-mail [email protected].
John Stirniman received his BSEE from the University of Illinois and his MBA from the University of Oregon. His experience includes seven years as manager for a process integration group at Intel Corp. and seven years as a development manager at ATEQ/ETEC. He is a cofounder of Precim Corp. and an engineering manager at Avant!
Behavior modeling compared to physical simulation
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Traditional TCAD simulation tools focus on semiconductor process development. "What if" experiments involving physical process parameters can be performed quickly to design and optimize wafer processes without time-consuming iterations in the fab. To do this accurately, physical models for all individual-contributing mechanisms must be employed in the simulation.
Behavioral modeling, on the other hand, focuses on capturing a snapshot of a stable process. By eliminating many degrees of freedom, computations required to render a behavior model simulation are considerably simpler than those needed for a complete physical model.
Behavior models are calibrated to empirical measurements taken from wafers to achieve accuracy equal to the best physical models. Calibrated behavior models are encapsulated in portable data files to be used for OPC, lithography verification, and interactive simulation.