An integrated etch approach as STI evolves for the 100nm regime
07/01/2000
Steve Lassig, C. Shan Xu, Alan J. Miller, Lam Research Corp., Fremont, California
Sanjay Kamath, Novellus Systems, San Jose, California
Andy Romano*, Takanori Kudo, Clariant Corp., Somerville, New Jersey
*Additional author is listed in Acknowledgments.
overview
As shallow trench isolation progresses toward the 100nm regime, numerous technical and manufacturing problems need to be resolved. The work presented here examines the current process parameter envelope, identifies problem areas, and develops an integration scheme that reduces process complexity and cost. The final scheme includes an integrated etch that could process hard mask opening, top corner rounding, and silicon trench etch in one pass. It also provides high-density oxide gap-fill that does not require annealing and can be planarized with direct-polish CMP.
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Figure 1. a) The top corner of the trench resulting from typical processes is shown relative to the position of the patterned nitride, which was used to define the active and trench areas. Note that with conventional processes, the rounded edge encroaches into the active area (i.e., under the nitride). The dotted lines represent the removal of oxide that occurs during the wet HF dips before the sacrificial and gate oxidation steps. These necessary dips expose the edge and lead to polysilicon wraparound. b) With the trench etch processes discussed in this article, the top corner rounding is improved. There is no encroachment, and the severity of the wraparound is reduced.
As the shallow trench isolation (STI) process approaches the 100nm regime, the most obvious trend is toward shallower trenches, with sub-200nm depths anticipated. Profiles are becoming more vertical, and CD bias control requirements are tightening, both of which require lower pressure processing and the use of high-density plasma etch systems. Currently, many fabs use a two-etcher approach to form the STI trench — one to etch the dielectric hard mask layers and another to etch the silicon after resist is removed. Older technologies required the trench sidewall to be tapered. The presence of resist during the more tapered silicon etches contributes to microloading that results in trench depth and profile variations between isolated and dense features, as well as between features of different widths. With steeper profile requirements, low-pressure processes allow an integrated approach to the trench formation. Advanced silicon etch systems are able to integrate the hard mask opening step in the same pass as the silicon etch, which results in higher throughput and reduced cost of ownership. Such processes are already in production.
Additional requirements are being placed on the STI module, including top corner rounding, high-aspect-ratio gap-fill, and direct-polish planarization. All of these are being implemented to reduce complexity and improve transistor performance. The first section of this paper will focus on the top corner rounding during the trench etch. The second section will concentrate on gap-fill, and the third part will take up direct-polish planarization. Finally, we will show the results of trench formation, gap-filling, and planarization capabilities for 100nm technologies.
Experimental approach
Two phases of experiments were conducted. The first investigated etch technology and integration of three process steps into one pass through the etch system. The steps integrated hard mask opening and the silicon trench etch, which are usually accomplished separately, while adding specific processes to round the top corners of the trench. Using a new lithographic technique called RELACS [1] provided by Clariant-AZ, we were able to define 100nm trench patterns on wafers that had 100Å of thermally grown pad oxide and 1000Å LPCVD silicon nitride. The wafers were then etched using a transformer-coupled plasma (TCP) etch system from Lam Research. All tests in this investigation were performed on 200mm wafers. The high-aspect-ratio gaps were filled using a Novellus SPEED HDP CVD tool.
The second phase of experiments concentrated on the implementation of direct-polish CMP. In conventional processes, the challenge is to flatten the topography evenly over areas that have varying pattern densities of trench and active areas [2]. Elaborate schemes have been devised to reduce dishing and erosion [3]. The most common method is the "reverse mask" approach that necessitates an additional masking and etch sequence. Other approaches, such as introducing dummy structures in wide trench areas, also lead to higher cost for manufacturing. In our studies, we used the Lam Teres CMP system and were able to planarize the wafer immediately after the HDP CVD fill step. The pad oxide was 100Å, and the nitride thickness was reduced to 1000Å, significantly below the typical 1600Å used in 250nm technologies. The trench fill oxide was varied between 20% and 50% overfill, while trench depths were varied (not including the dielectric layers) between 350nm and 550nm. By minimizing the thickness of the depositions, throughput is increased in both the deposition and CMP tools. For each of the four split lots used in this experiment, wafers were polished for different amounts of time and subsequently examined using a Tencor UV1250 for film thickness measurements. Post-CMP step heights were measured using a Tencor P-11 profilometer. Selected samples were also cross-sectioned and inspected with a scanning electron microscope (SEM). The layout of the reticle used allowed us to investigate an extremely wide range of structures, which included isolated features from 1mm x 1mm to 4000mm x 4000mm, pattern density arrays from 20-80% (active area), and trenches up to 1000mm wide.
Etch module: Top corner rounding
The abrupt transition from active area to the trench can be a source of parasitic transistor characteristics. When this corner is sharp, polysilicon wraparound causes a separate conduction path that results in the so-called "double-hump" in the I-V characteristics [3-5] and reverse narrow channel effects [5]. Several techniques have been investigated to provide the required 30-50nm corner rounding to ameliorate these problems. Current methods reduce the electrical width of the transistor due to the encroachment of the rounding into the active area [3]. As we approach the 100nm regime, this reduction can represent a high percentage of the transistor width.
This issue is addressed using a new top corner rounding technique that is accomplished during a short etch step after the nitride hard mask is opened and before the silicon trench etch is performed. This lends itself to both in situ and ex situ hard mask opening schemes and adds virtually no cost to the processing.
By providing the top corner rounding during the etch, we eliminate the encroachment and reduce the severity of the effect of polysilicon wraparound. Figure 1 on p. 157 shows the difference in the resulting structure after the several wet oxide removal steps needed before the sacrificial and gate oxidations. It should be noted that the corner is less exposed after the same amount of oxide removal. Also, the top corner is rounded without encroachment. Figure 2 shows the trench after etch with nitride still in place to show the location of the rounding with respect to the active area delineated by the nitride edge. With current techniques such as high-temperature oxidation, the rounding would be located below the nitride. Several chip-manufacturing development groups have investigated this technique and found reduced threshold variation, as shown in Fig. 3.
Fill module: HDP CVD for void-free dense dielectric
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As trench widths decrease, trench aspect ratios increase. Increased aspect ratios, plus the fact that filling takes place while the nitride layer is still in place, exacerbates the problem of furnishing a dielectric fill without voids. Structures with a spacing smaller than 150nm and an aspect ratio higher than 5:1 have previously been filled using a Novellus SPEED HDP CVD system [6] with a silane-and oxygen-based technique that makes use of simultaneous etching and deposition [7]. To minimize nitride edge faceting, the etch-to-deposition ratio must be kept relatively low, which reduces the gap-filling capability. This is primarily corrected by lowering the deposition pressure [6].
A higher deposition temperature (~650°C) is also found to improve gap-fill performance [8]. Depositing from oxygen and silane in this temperature regime also results in a very dense film. Consequently, subsequent anneals will not cause significant volumetric expansion or contraction that could lead to dislocation damage in the etched silicon trenches. Figure 2 shows 100nm
features with aspect ratios of ~3.5:1 that were filled without voids.
CMP module: Direct-polish planarization
In this phase of the study, the trench depths were split between 350nm and 550nm. These were chosen to cover the upper limit of depths that may be considered for advanced applications. As trench depths decrease, the job of planarization becomes easier. Note that the dielectric layers increase the depth by their combined thickness (~110nm), so the actual trench depths for fill and planarization were 460nm and 660nm, respectively. The wafers were further split for deposition thickness as a percent of the total trench depth (see table).
Wafers from each split were subjected to various removal times using Lam's Teres CMP system. This system has proprietary linear planarization technology, which replaces the traditional rotating platen with a linear polishing belt [9, 10]. The CMP was performed using direct-polish immediately after deposition (i.e., with no densification). Completion was defined as the time to remove all traces of oxide from large (2000mm x 2000mm) nitride (active) areas. This pushes the limits of what would be used on typical device wafers, but we wanted to understand the limits of the technology. Figure 4 shows the step height or dishing vs. polish time for wide trenches (>200mm) from wafers that had 350nm-deep trenches (460nm including nitride) and were 50% overfilled. Also included is the nitride erosion of very small (more sensitive) active regions. These data clearly show a wide process window with excellent planarization capability. Note that the completion time as previously defined was 90 sec for this split.
 Figure 5. Variations in step height for the four splits show that pattern sensitivity becomes less severe with shallower trench depth and increasing overfill. |
Figure 5 shows the step-height variation seen between structures whose pattern density varied between 20% and 80%. The data for this plot was taken at a time ~10% beyond the point of completion as previously defined to better represent a manufacturable process. As the trench depth is decreased and the overfill is increased, the resulting variation due to pattern density is reduced. The splits using 50% overfill showed superior results compared to the 20% overfill, and the difference was greater for the shallower trenches. In order to increase throughput and decrease cost for deposition and CMP, this kind of analysis should be carried out for trench depths in the range of 200-250nm for future technologies.
Figure 6 shows cross-section micrographs of the ends and middle of a 1000mm-wide trench. This clearly illustrates the success of the direct-polish approach over wide isolation areas. The amount of dishing is about 100Å.
It is estimated from trends in the current work that overfill can be reduced to ~35% (i.e., ~5000Å HDP CVD), and that CMP polish time can be reduced to approximately 60 sec for 100-130nm technologies while improving performance. We also believe that nitride thickness could be reduced to 800Å, which would further improve the planarity. This would require the in situ trench etch approach and would reduce the recess oxide wet etch requirements needed to manage step-height variation between active and isolation regions after nitride was removed.
Conclusion
To achieve the packing density and device functionality that future designs will require, STI will become a required technology. As the industry moves toward the 100nm regime, issues about trench encroachment and process complexity (cost) will become more problematic. Specific integration schemes utilizing top corner rounding that have limited or no encroachment, voidless gap-fill in the increasingly narrow trenches with high-quality dielectric, and direct planarization will be paramount considerations. Through joint development efforts, our team has shown one integrated and cost-effective process sequence that addresses these issues. The technology for 100nm capability is in place.
Acknowledgments
Takanori Kudo of Clariant Corp. is an additional author of this work.
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Steve Lassig received his BS and MS in materials engineering from Rensselaer Polytechnic Institute. He has 18 years of experience in the semiconductor industry, has been awarded several patents, and has contributed to more than 16 technical publications. In 1990, Lassig joined Lam Research, where he is a senior manager of process integration. Lam Research Corp., 4650 Cushing Parkway, Fremont, CA 94538; ph 510/572-3787, fax 510/572-6588, [email protected].
C. Shan Xu received his PhD in physical chemistry from the University of California, Berkeley. He is a principal scientist for Lam Research Corp's. CMP/Cleaning Products Group, and has worked on STI, PMD, ILD, W, Cu, and Si CMP applications and consumable development.
Alan J. Miller received a degree in mechanical engineering from the University of California, Berkeley, in 1984. He has more than15 years' experience in the semiconductor equipment industry, and is a senior staff process engineer at Lam, where he has worked for the last 13 years. Miller has worked extensively on silicon etch process development.
Sanjay Kamath received his BE in electrical engineering from Manipal Institute of Technology in India, his MS in electrical engineering from the University of Tennessee, and his ME in microelectronics manufacturing from the Rochester Institute of Technology. He is a member of the Dielectric Business Unit at Novellus Systems.
Andy Romano received his MS in chemistry from Wayne State University, Detroit, MI. He founded and was chairman of the SPIE Photolithography Working Group in 1993; in 1994, he joined the Fairchild Research Center at National Semiconductor. Romano moved to Clariant in 1998 as product manager, advanced products.