Process development and monitoring with atomic force profiling for CMP
07/01/2000
Tim Cunningham, Brad Todd, Digital Instruments Veeco Metrology Group, Santa Barbara, California
Jayashree Kalpathy-Cramer, Eric Kirchner, Michael Berman, LSI Logic Corp., Gresham, Oregon
overview
CMP processes are being used in an increasing number of applications in the wafer fab in response to shrinking device geometries with their increased need for planarity. There is a corresponding growing need for measurement of post-CMP parameters over lengths from device size (<1mm) to die size (>10mm). Measurements required for process development and production monitoring include plug recess, dishing around lines and plugs, erosion in patterned areas, and planarity across the die. A new instrument, combining capabilities of stylus surface profilers and atomic force microscopes, has been developed specifically for this purpose.
 Figure 1. Diagram showing the profiling stage (profile drive) and Metrology AFM head on the Vx atomic force profiler (AFP). |
Chemical mechanical polishing (CMP) is one of the most rapidly growing areas of the semiconductor industry thanks to its ability to provide global planarization for a wide range of submicron processes. In parallel, characterization of CMP is increasingly important in both process development and production monitoring for deep submicron device manufacturing. The small feature sizes involved in these processes place stringent requirements on CMP characterization and metrology equipment.
 Composite of Atomic Force Profile and ASM images. |
Increasingly, process developers and engineers are requiring nondestructive topography measurement tools capable of measuring over die-length distances (~10mm), with resolution capable of measuring internal features of structures whose total extent is 130nm and less. The International Technology Roadmap for Semiconductors (ITRS) [1] predicts that microscopy with 1nm resolution will be required by 2001. Resolution as defined by the 1999 ITRS Roadmap is the ability to resolve differences between structures with a precision-to-tolerance ratio of 0.1 (P/T = 0.1). An example from the ITRS illustrates this. The minimum gate width is predicted to be 100nm in 2001, and the stated process tolerance (the T in P/T) is ±9nm. This means that a capable metrology tool must repeatably measure a ±0.9nm dimension change or, in other words, have a precision of 0.9nm (the P in P/T). Published specifications for AFM profilers indicate that 0.5nm precision is possible on a 100nm tall etched feature.
Semiconductor manufacturers look to the extendibility of metrology techniques and carefully weigh the technology roadmap for these tools relative to their internal requirements for geometry shrinks. A recent report from Texas Instruments indicates that TI has shrunk, and will continue to shrink, devices by 70%/year for the foreseeable future [2]. This means that metrology tools must meet requirements of current technology and for several generations down the road in order for the systems to have a significant useful life in the fab. Recent microprocessor announcements indicate that leading edge suppliers will continue to require process and metrology equipment in advance of the 1999 ITRS Roadmap. This raises the possibility that the unprecedented pace of geometry reductions observed since 1996 will continue with the 130nm node being pulled into 2002. For this reason, new purchases of metrology equipment will face stringent requirements to demonstrate capability in advance of the Roadmap, and must qualify on development devices several generations in advance of those going into production this year.
Three application examples of the atomic force profiler for CMP or CMP-related processing are given to demonstrate process variation issues and metrology capability:
1) post-CMP dishing and erosion on damascene processed Cu lines,
2) effect of slurry particle phase and size in tungsten CMP, and
3) STI process development and monitoring.
Description of the AFP
A Veeco Instruments Vx atomic force profiler (AFP) was used to make the measurements shown in this article. The tool is configurable for 200mm or 300mm wafers and can perform AFM scans up to 65mm x 65mm, and profiles up to 100mm long anywhere on the wafer surface. A schematic diagram of the measurement system is shown as Fig. 1. The AFP was developed to take advantage of features of both stylus profilers and atomic force microscopes. The long scanning capability typical of stylus profilometers is needed for die-size features important in CMP characterization. Added to this is the ability of atomic force microscopes to resolve subnanometer changes in die topography. As film stacks shrink in the future, the process window for CMP-related dishing, erosion, and recess continues to diminish. The AFM mode used for measurement on this instrument is nondestructive to semiconductor devices because the tip force is applied only normal to the measured surfaces and is less than the force required to displace atoms in the surface.
 Figure 3. Erosion depth vs. line width in post-CMP Cu test patterns. |
Atomic force microscopy encompasses at least four specific modes of operation characterized by the way in which the tip interacts with the measured surface. The feature of atomic force microscopy that differentiates it from stylus profiling is that the tip radius is sharp enough to allow sensing of the atomic force interactions between tip and sample. Feedback control for atomic force microscopes or profilers is sensitive to the interaction forces between electron shells of the tip and the sample. The approach of the tip to the surface is controlled to within the scale of chemical bonds, typically a few angstroms, depending upon the type of atomic force microscopy being performed. Prerequisite to atomic force microscopy is cantilever control sensitive to these atomic interactions and fast enough to respond to them. The four categories operate in either the attractive mode or the repulsive mode, depending on the distance of the tip approach. The cantilever that holds the tip as it is moved over the sample surface can be either static or driven at its resonance frequency.
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The four modes of AFM operation are attractive static, attractive dynamic, repulsive static, and repulsive dynamic. The repulsive dynamic mode, a patented method ("TappingMode"), is the mode used in the applications described in this article. In this mode, the cantilever and tip are driven at their resonant frequency (~100kHz). The instrument holds the cantilever amplitude constant by maintaining the distance between sample and tip constant as the tip 'taps' the surface. The lateral and vertical dimensions of sample features are observed by closely monitoring the motion of the cantilever and tip as they scan over the surface. Advantages of this method include high traverse rates, subnanometer resolution, and purely normal forces on the sample. Normal forces on the sample allow nondestructive metrology on semiconductor surfaces, because the atomic displacements of sample atoms do not exceed the elastic limits of the atomic bonds.
The sensor head itself is an AFM specifically designed for highly repeatable metrology measurements. In addition to its linear profiling capability, the AFP incorporates all of the functionality of the AFM, specifically its ability to execute high resolution raster scans up to 65mm x 65mm square. All drives and the sensor apparatus are mounted on a rigid structure that is isolated from floor vibrations. A framework around the isolated structure supports acoustic damping panels that enable the tool to be used in the typically noisy cleanroom environment.
Sampling density is high enough for die length profiles to be made with sufficient resolution to zoom in and view fine features in the same profile without re-measurement. Each profile consists of up to 262,000 data points with a DSP sampling rate of ~20kHz. Thus, for example, a 10mm profile will have a sample density of 26.2 samples/micron (corresponding to 38nm spacing between data points). Profiling speeds range up to 200mm/sec, and the usable speed for a particular sample is determined by specifics of feature size and spacing. High resolution is maintained by using tips with 5-10nm radius. The AFP uses the same tip in both profiling and imaging modes. The same tip type, tapping etched silicon probe (TESP), was used for all measurements presented here.
The metrology AFM head incorporated in the Vx AFP has been designed to maintain the tight limits on axis orthogonality, flatness of the xy plane, linearity, accuracy, and repeatability required for CMP and other demanding metrology applications. This metrology head incorporates highly precise closed-loop position sensors to monitor the tip position. The proprietary design of the piezo stages results in a very flat xy scan and perpendicularity of <0.1° between the axes. The head can also be used in open loop mode for measurements for which a lower noise floor is required, such as measurement of roughness down to <0.5nm.
The Vx AFP is configurable for 200mm or 300mm wafers, with or without automatic tip exchange, and with a variety of front-end options including a SMIF i/o unit with better than Federal Class 1 particulate levels throughout the system.
Post-CMP planarity and erosion on damascene Cu lines
The AFP was used to characterize a post-CMP Cu damascene processed sample [3]. The 200mm wafer contained Cu line structures of varying width and pitch. The trenches were filled using an electroplating process, after which all excess Cu on top of the interlayer dielectric was removed by CMP. Long range profiling was used to characterize dishing and erosion effects on this wafer.
Figure 2a on p. 168 shows a 21.5mm-long profile crossing four test structure patterns within a single die. All test patterns were 2.5mm across, each with a different combination of trench width and pitch. Trench width and pitch increase from left to right in the profile. The total indicated runout — the vertical distance from maximum to minimum — across this particular die was 330nm. Several devices were examined, incorporating test patterns with a variety of trench widths and pitches, but all patterns had a width-to-pitch ratio of either 1:2 or 1:3.
Figure 2b shows the zoomed (6mm in length) and leveled profile of the leftmost test pattern in Fig. 2a, demonstrating that step height can be measured on the eroded structure without re-scanning. Average step height was measured from the center region of the eroded structure to the dielectric immediately adjacent to the structure. The data indicates that the significant variable for erosion in the trenches was the trench width-to-pitch ratio. Structures with a width-to-pitch ratio of 1:3 exhibited a clear increase in erosion with trench width. The trend is much less pronounced for trenches with width-to-pitch ratio of 1:2. (See Fig. 3.)
Figure 2b clearly shows that the sample is over-polished (shown as a deeper recess) in the transition regions between the upper dielectric and the Cu-filled trench patterns. The additional recess (over the average erosion of the Cu trench pattern) is ~30nm. Figure 2c is a blow-up of the transition area in Fig. 2b. Individual Cu lines are clearly resolvable in the 25mm length.
This example shows the classic process control issues for CMP: long-range dishing, feature erosion, and geometry dependent etch rate. The AFP demonstrates both the long scan capability and the ability to resolve fine detail without rescanning. Figure 2c shows z-height detail as small as 2nm from the original 21.5mm profile.
Effect of alumina slurry particle size in tungsten plug CMP *** As part of a larger study of the role of alumina slurry particle phase and size in tungsten CMP [4], three experimental slurry formulations produced by Ferro Corp. and a commercially available proprietary alumina and potassium iodate slurry were compared. All four slurries had relatively high polish rates on blanket tungsten films. The Ferro slurries were all prepared with identical potassium iodate and hydrogen phthalate chemistry. Particle size and average tungsten film polish rate are summarized in Table 1.
Identically patterned wafers (metal 1/via/metal 2) were polished with each of the four slurries, under identical conditions of pressure and relative velocity. Figure 4 shows an AFM image of the tungsten plug field produced by each slurry.
 Figure 4. AFM images of post-CMP tungsten plugs. The z-axis is 20mm tall. |
SRS187 and the baseline slurry showed formation of tungsten studs, with no evidence of keyholes or corrosion. SRS188 and SRS189 slurries produced tungsten plugs that were more nearly co-planar with the oxide layer, but which also included more keyholes. None of the slurries produced appreciable dishing around the plugs. The experimental slurries evidently left a greater number of slurry particles on the surface than the baseline slurry did. Particles are visible as small spikes in the AFM images.
The average erosion step height, measured by profiling from a 4mm x 4mm array of tungsten plugs to an adjacent 4mm x 4mm oxide square is noted for each slurry in Fig. 4. The smaller particle slurries (SRS187 and baseline) produced more erosion than the larger particle slurries (SRS188 and SRS189). This example illustrates the quantitative capability of the AFP and the ability to provide images that show process variation.
STI process development and monitoring: Roughness and planarity
Atomic force profiling was used as part of a CMP process evaluation for shallow trench isolation (STI). The step heights in STI are critical because the planarity affects polysilicon pattern definition, and steps can lead to poly stringer formation [5]. Surface roughness is also important because it indicates defects associated with scratching, and it also affects the morphology, and thus reliability, of subsequently deposited layers.
The data presented below were gathered using a single tip type. The step heights were measured on 450mm profiles of a test structure, while the surface roughness was extracted from 2mm square AFM scans. An example of the test structure is shown as Fig. 5a, and Fig. 5b is the same profile, expanded on a feature of interest. Figure 6 is a 2mm x 2mm AFM scan on the pad surface, with on-line roughness analysis results in the right side of the figure.
Repeatability of some measurements was determined by multiple runs of automated recipes that performed pattern recognition and alignment, then data collection of the profiles or AFM scans at various sites on the wafer. The repeatability represented in the data below is one standard deviation from the repeat measurements at each site.
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The first set of data, Table 2, show the surface roughness for three different CMP processes. All three processes show consistently low roughness. The repeatability data indicates standard deviations around 0.02-0.06nm, so it is difficult to state that there is a significant difference between the processes, or between the wafer locations. The repeatability is tight, though, and it puts the measured values significantly above the noise floor of the tool.
 Figure 5. Relative height of a) 450mm long profile of a test structure, and b) a zoom-in on a 2mm wide line. |
Table 3 shows steps heights of an STI feature before and after CMP. The reverse tone etch assists the planarization, but planarity can become worse as nitride is exposed due to the selectivity of the process. These results show the usefulness of this measurement as a process monitor. The step height of the first wafer is fairly consistent across the wafer, but the second wafer shows that the process is unstable at the wafer edge, leading to significantly higher steps. This critical information cannot always be extracted from typical inline thickness measurements, as these types of measurements can be confounded by integration aspects of the various steps in the STI process. The repeatability of these measurements consistently shows <1nm variation for steps as small as 2nm and as large as 60nm.
The final set of data, summarized in Table 4, was measured on a single wafer as it was processed through the STI module. The automation allows a recipe that can align to the wafer pattern and perform the same measurements at each of the process steps. This kind of information is extremely useful in developing and integrating processes into a fabrication flow. It makes it easier to understand the impact of a process change on other process steps, and the final product.
Conclusion
 Figure 6. Roughness measurement over 2mm x 2mm area oxide in the trench. |
These application examples illustrate different capabilities of the new type of profiler. In each case, the AFP provides data with sufficient resolution to identify significant variation of device structures after CMP processing. Significant conclusions were drawn concerning process variation across a wafer, across a die, and on individual features. It is clear from the size of the variations observed in these examples that CMP processing faces significant challenges considering the rate at which film thicknesses are being reduced.
The continuing ability of CMP processing to enable the shrinking of lithographic dimensions and to reduce process steps relies upon the capability of metrology to observe significant variations. Competitive requirements to extend the life of fab equipment through multiple geometry shrinks and technology nodes mean that metrology for many CMP process levels must not only meet today's requirements but must also be extendable to the 130nm node and possibly to the 100nm node. The AFP is proving to be well suited to meet this requirement for extendibility.
Acknowledgments
The authors wish to acknowledge the contributions of Larry Ge, now of Intel Corp, and Kevin Kjoller for acquiring and processing much of the data in this paper; and David Stein of Sandia National Laboratories and Bob Her of Ferro Electronic Materials for their kind permission to use data they acquired during Vx AFP beta testing at Sandia Microelectronics Laboratory.
References
- Semiconductor Industry Association, International Technology Roadmap for Semiconductors: 1999 Edition, Austin, TX: International Sematech, 1999.
- R. Helms, "Fab-wide Automation is Critical to Microelectronics' Future," Solid State Technology, p. 49, January 2000.
- L.M. Ge, T.M. Cunningham, D.J. Dawson, F.M. Serry, M.J. Heaton, "Atomic Force Profilometry for Characterization of Chemical Mechanical Planarization Process," Proceedings of the 1999 CMP-MIC Conference, p. 79, 1999.
- D.J. Stein, R.L. Her, "Role of Alumina Phase and Size in Tungsten CMP," Proceedings of the 2000 CMP-MIC Conference, p. 39, 2000.
- M. Berman, J. Kalpathy-Cramer, E. Kirchner, R.L. Opila, et al. (eds.), in Chemical Mechanical Planarization in IC Device Manufacturing III: Proceedings of the International Symposium (Pennington, NJ: The Electrochemical Society), p. 22, 2000.
Tim Cunningham received his BS in engineering physics from the University of Colorado. He has been with Veeco metrology group for four years and is currently the atomic force profiler program manager. He previously developed metrology tools for the flat panel display and semiconductor industries, and diagnostic instrumentation for a variety of research applications. Digital Instruments/Veeco Metrology Group, 112 Robin Hill Rd., Santa Barbara, CA 93101; ph 805/967-2700, fax 805/967-7717, e-mail: [email protected].
Bradley Todd is the strategic marketing manager for Veeco Instruments semiconductor product group in Santa Barbara, CA. His responsibilities include next generation equipment specification for atomic force metrology and industry partnerships for metrology solutions. Previously he worked for IBM ASTC as a DUV lithography process engineer and was part of a team that designed and built the ASTC in East Fishkill, NY. In 1990, he obtained an MS degree in microelectronics manufacturing from Rensselaer Polytechnic Institute.
Jayashree Kalpathy-Cramer received her PhD in electrical engineering from Rensselaer Polytechnic Institute. After developing CMP slurries for aluminum as a post-doc there, she moved to LSI Logic's R&D facility in Santa Clara. She now works at LSI Logic's Gresham, OR fab developing new technology modules involving CMP.
Eric Kirchner received his PhD in materials engineering from Rensselaer Polytechnic Institute in 1996. He was hired as a CMP process engineer to start up LSI Logic's new Gresham, OR fab. He now works there on CMP process development and integration.
Michael Berman is currently the section manager for CMP for LSI Logic's new fab in Gresham, OR. He has a BS in physics, eight US patents, and has written or co-authored more than a dozen technical papers.