Processing for advanced devices with hot-wall furnace RTP
07/01/2000
OVERVIEW
A new single wafer hot-wall isothermal furnace RTP system incorporates many benefits of large batch furnaces while satisfying throughput and thermal budget constraints motivating an industry migration towards single wafer processing. The system is capable of producing wet and dry oxides, with and without chlorine. A quartz process chamber makes it compatible with chlorine processes. Oxidation or anneal processes in NO or N2O can be performed to produce nitrided gate oxides, and numerous CVD applications are possible. The hot-wall isothermal process chamber reduces emissivity problems, and a stacked process chamber configuration contributes to efficient fab utilization and sequential processing capability for gate stack and capacitor structures.
This paper discusses the benefits of large batch furnaces, the advantages of single wafer processing, and how a single wafer furnace incorporates these benefits and advantages while overcoming drawbacks of single wafer lamp-based RTP systems. Silicon Valley Group's Furnace RTP is the system used for these evaluations.
Traditional furnaces
One of the main reasons that silicon was chosen as the preferred semiconductor substrate material is the ease of growing a stable insulating layer of oxide on it in a furnace. In particular, controlling the interface between silicon and silicon dioxide was crucial for MOS to become the mainstream device technology.
 Process module of the new single wafer furnace system, Xcelerate, from SVG Thermal Systems. |
The performance of advanced MOS devices is largely determined by the gate dielectric. This film, traditionally silicon dioxide thermally grown in a furnace, is well documented and understood. At atmospheric pressure, dry oxides are grown with oxygen, and wet oxides are grown with steam. The steam is typically generated by the pyrogenic reaction between oxygen and hydrogen in an external torch prior to being introduced into the process chamber. The electrical properties of the gate are very sensitive to low levels of metallic contamination. Chlorine is periodically introduced into the process chamber at elevated temperatures, either as gas phase HCl or nitrogen bubbled through a liquid chlorine source. The chlorine serves to getter metallic contamination that may otherwise be incorporated into the wafers during subsequent processing and have adverse effects on device performance. Many wafer manufacturers include a chlorine source during the actual oxidation to improve the quality of the oxide, in addition to using periodic chlorine steam cleans.
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Advanced gate dielectrics use "nitrided" oxides. These can be thermally grown oxides that are nitrided with a subsequent, typically in situ NO or N2O anneal, or oxides grown in NO or N2O ambients. The nitridation of the gate oxide improves the electrical properties of the film and helps to prevent boron diffusing from the gate polysilicon to the gate region in the substrate [1].
Thin films such as silicon nitride, silicon oxynitride, silicon oxide, intrinsic or doped amorphous silicon, and polysilicon are deposited in low-pressure chemical vapor deposition (LPCVD) furnaces.
Advantages of single wafer processing
The two predominant motivators driving the industry toward single wafer processing are thermal budget and cycle time.
From a technical perspective, the long temperature ramps and time at temperature inherent in traditional batch furnaces exceed the thermal budget constraints of the extended source and drain components of a transistor structure [2].
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Economically, there is continuous pressure on semiconductor manufacturers to reduce cost by improving efficiency of the wafer fab. Semiconductor manufacturers typically run lots of 25 wafers through the fab. Batch furnaces typically run loads of 100-200 wafers (4-8 lots) per pass. The first lot to reach the furnace operation usually has to wait for sufficient lots requiring the same recipe before it can be processed. After the furnace operation, all of the wafer lots are queued at the next piece of equipment, which is typically a single wafer system, where they wait their turn to be processed. This occurs at several steps throughout the wafer flow. If the large batch process is replaced with a single wafer tool, wait and queue time are dramatically reduced. The process cycle time is also much shorter.
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An oxidation process in a typical 150-wafer batch furnace with a cycle time of 3 hrs can be run on the single wafer furnace RTP with a cycle time of 2 min/chamber. For this process, the furnace throughput is 50 wafers/hr compared to the SVG single wafer furnace RTP throughput of 120 wafers/hr.
Single wafer processing therefore reduces WIP, shortens cycle time, and improves fab efficiency. Similarly, reduced cycle times are being driven by shorter product life cycles, which necessitate shorter time to market and faster cycles of learning.
Additional technical benefits of single wafer processing include process integration processing and improved uniformity. In large batch loads, the wafers are stacked close together. Within-wafer uniformity for mass-transport limited reactions, which are sensitive to wafer spacing, is compromised. Maintaining good wafer-to-wafer uniformity across a large batch can also be a challenge. As technology advances drive smaller critical dimensions, some applications require thinner film thicknesses with overall uniformities that challenge the capabilities of large batch furnaces.
Despite the advantages of single wafer processing, low cost of ownership has made large batch furnaces an attractive alternative in many applications, compared to conventional lamp-based RTP systems, which have a higher cost of ownership. The single wafer furnace combines the flexibility and reduced thermal budget of single wafer processing with the low cost of ownership of large batch furnaces.
Traditional RTP
Traditionally, RTP systems are lamp-based, cold-wall reactors. Wafers are heated via radiation, usually from tungsten halogen lamps. One of the drawbacks of lamp-based heating is the high peak power consumption during the temperature ramp. Lamp-based systems consume 3-4 times the peak power of resistively heated furnaces [3]. The transfer of energy from the lamp-based heat source to the wafer is strongly dependent on the emissivity of the absorbing film. As the wafer progresses through the fab, the wide variety of films on the surface with different emissivities can lead to inhomogeneous absorption of radiation. As a consequence, temperature measurement and control have been a persistent challenge with lamp-based systems [4].
Traditional RTP systems are not able to duplicate the high quality of furnace grown gate dielectrics. Many single wafer tools cannot perform oxidation in steam or grow dry oxides in a chlorine ambient, and most are not able to make use of high temperature steam cleans with a chlorine source to minimize metallic contamination. Many single wafer tools have not been able to match the low level of metallic contamination required for advanced gate dielectrics due to the large amounts of metallic materials used in the construction of their process chambers.
Furnace RTP
The Furnace RTP was designed to include the benefits of the large batch furnace, in conjunction with the advantages of single wafer processing. These benefits include an isothermal processing environment, superior temperature control, and nonmetallic chamber components. Advantages over large batch furnaces that have been designed into the Furnace RTP include more control over process chamber gases, and improved heat flux uniformity to the wafer surface.
The process chamber consists of a quartz process tube surrounded by a multizone resistive heating element, and it is well insulated to ensure that the reaction zone is isothermal. A silicon carbide blackbody radiator is enclosed inside the process chamber. The combination of symmetric, strategically placed heating zones, along with the silicon carbide thermal diffusion plate, allows the system to achieve excellent thermal uniformity in the upper portion of the process tube.
 Figure 6. SIMS plots of a) N2O anneal at 1000°C and b) NO anneal at 1050°C. |
The wafer is heated by elevating it from a lower cold chamber to an upper hot chamber, where it is placed in close proximity to the thermal diffusion plate. During the ramp-up, the wafer is heated at rates in excess of 100°C/sec. Since the process chamber is an isothermal black body, wafer temperature is independent of emissivity. As can be seen from Fig. 1, only the ramp rate is affected by emissivity, not the process temperature. This resolves a significant impediment to lamp-based systems where wafer emissivity affects temperature measurement and control. Furthermore, it is not possible for the wafer temperature to overshoot the temperature of the diffusion plate, in contrast to systems where the tungsten halogen lamps ramp at temperatures significantly higher than the wafer setpoint.
Quartz shutters thermally isolate the hot and cold chambers. The shutters open and close only as the wafer passes from chamber to chamber. By isolating the hot and cold chambers, better thermal uniformity in the process area is achieved, and the energy efficiency of the system is enhanced. The energy consumption of a hot-wall system is much less than that of a lamp-based system, and peak power requirements are also greatly reduced.
Uniform wafer temperature during ramp and steady state is made possible by transporting the wafer in a quartz wafer holder with custom features that minimize edge-to-center temperature differences. If the radial delta temperature (RDT) is not controlled, expansion differences between the edge and center of the wafer can generate sufficient force to cause the crystal lattice to slip. Temperature data taken using a thermocouple instrumented wafer indicates that RDT is well below the slip curve, and no evidence of slip is observed on the processed wafers. Slip was evaluated with a Hologenix metrology system.
The wafer is exposed to a cross flow of process gases only in the upper portion of the process tube. The cross flow is a laminar plug type flow, which allows quick transition from one gas species to another. The injector plenum is designed to give uniform flow distribution across the wafer surface. The uniformity and flow laminarity have been substantiated by flow visualization studies. The system incorporates wafer rotation, which aids in thermal uniformity as well as improving the gas distribution across the wafer.
An advantage of this system is that all of the parts that are exposed to process gases are made of either quartz or silicon carbide. This provides the capability of performing high temperature steam cleans with a chlorine source for improved removal of metallic contaminants, as well as chlorine oxidations.
Sequential processing in multiple process chambers can generate composite films that are needed for gate stacks and capacitor structures in current and future devices. For example, a conventional gate may be created by a thermal oxidation / NO anneal / polysilicon deposition process sequence. An advanced gate stack may be the result of NO oxidation / nitride deposition / nitride oxidation / polysilicon deposition. A memory cell node may be created by thermal oxidation / nitride deposition / deposited HTO (high temperature oxide) / polysilicon deposition. An advanced capacitor node process could be NH3 anneal / nitride deposition / nitride oxidation / polysilicon deposition.
All of these processes could be run on one Furnace RTP system, providing the ability to bridge device generations in a production environment, or provide versatility for fab development.
Experimental results
 Figure 7. Modeled comparison of radiative and conductive heat transfer for different gaps between the thermal diffusion plate and the wafer. |
High quality gate oxides with a thickness range of 20-40Å have been grown using both wet and dry oxidation ambients, with and without HCl. The ability to perform HCl-assisted steam cleans allows for improved removal of metallic contamination, down to less than 1010atoms/cm2, compared to a typical 3x1010atoms/cm2 for a lamp based RTP tool. This translates into better dielectric breakdown characteristics, which are crucial for thin gate oxides [5]. Uniformity for thin wet oxides is typically 0.5% (1s) for 35Å films, and 0.6% (1s) for 25Å. Steam grown oxides demonstrated growth rates of 100Å/min at 900°C. Uniformity for 35Å oxides with 3% HCl is typically 0.7% (1s) for wet oxides, and 0.8% (1s) for dry oxides. Uniformity for oxides with NO or N2O anneals and a final thickness of 40Å is typically 0.5% (1s). Examples are shown for 200mm wafers (Figs. 2-5). These uniformity maps are typical and compare favorably to traditional furnace results.
Oxides annealed in N2O or NO had peak nitrogen incorporation levels of 0.5-5.1 atomic percent, depending on anneal temperature, ambient, and time (Fig. 6). This is significant because it shows that nitrogen content, which improves oxide integrity and is critical for inhibiting boron diffusion, can be tailored.
In addition to silicon nitride and polysilicon, (discussed previously as components in sequential composite films), other CVD applications include oxynitride, deposited silicon oxide, and intrinsic and in situ doped amorphous silicon.
Lamp-based cold-wall systems use silane as a silicon nitride precursor, in contrast to large batch furnaces, which produce higher quality films with dichlorosilane (DCS). Cold wall systems cannot use DCS because the ammonium chloride, which is a byproduct of the reaction with DCS, condenses in the cold regions of the chamber and generates particles. Since the Furnace RTP is a hot wall reactor, ammonium chloride condensation is not an issue, and films with better conformality, less stress, and lower hydrogen concentration can be deposited.
A single wafer furnace RTP system also has advantage of lamp-based systems for low temperature anneals. The absorption of radiative energy by silicon is poor at temperatures of less than ~600°C. This is due to the small amount of active free carriers in silicon at low temperatures. Because of this, the achievable ramp rates and temperature control of lamp-based systems are poor at low temperatures. The conductive heat transfer between the thermal diffusion plate and the wafer is much more efficient than lamp-based radiative heat transfer (Fig. 7). Consequently, low temperature processes such as copper, low-k dielectric deposition and anneals, and metal alloy anneals are well suited to this kind of furnace.
The Furnace RTP can also be used for ion implant activation anneals. After ion implantation, the implanted dopant species needs to be activated. Higher anneal temperatures activate more of the dopant. Due to fast ramp rates, the Furnace RTP is able to activate implants at high temperatures while maintaining thermal budget requirements.
Borophosphosilicate glass (BPSG) is conventionally used as a pre-metal dielectric and requires an anneal after deposition. The isothermal black body chamber is insensitive to outgassing during these BPSG anneals, which tends to cloud lamp and pyrometer windows, resulting in temperature control difficulties and a consequential degradation of wafer-to-wafer and run-to-run anneal uniformity for lamp-based systems.
Similar to the large batch furnace, the single wafer furnace offers lower cost of ownership than lamp-based single wafer tools. Furnace technology is highly reliable — traditional heater elements, rather than lamps, reduce consumables, and power consumption is much lower.
Conclusion
The system discussed here is a single wafer hot-wall isothermal furnace, which incorporates many benefits of large batch furnaces while satisfying throughput requirements and thermal budget constraints. Compatibility of the quartz process chamber with chlorine yields oxides of superior quality to those grown in conventional lamp based systems. Emissivity insensitivity of the hot wall isothermal process chamber eliminates problems associated with wafer temperature measurement and control inherent in traditional lamp-based RTP systems.
Acknowledgments
The authors would like to recognize the contributions of Aubrey Helms, Jr., Chris Ratliff, and Rich Tauber to this work.
References
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- P. Timans, "Temperature Measurement Strategies for Rapid Thermal Processing in Semiconductor Manufacturing," Rapid Thermal Processing '96, ed. by R.B. Fair et al., pp. 145-155, 1996.
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- T. Yang, K. Saraswat, "Effects of Physical Stress on the Degradation of Thin SiO2 Films Under Electrical Stress," IEEE Transactions on Electron Devices, Vol. 47, No. 4, pp. 746-754, April 2000.
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Nick Osborne received his BS in physics from London University and his MBA from the University of Phoenix. He has more than 20 years of experience working in the semiconductor industry, primarily in the wafer fab. For the past five years, he has been a product marketing manager for Silicon Valley Group, 440 Kings Village Rd., Scotts Valley, CA 95066; ph 831/439-6407, fax 831/439-6223, e-mail [email protected].
Allan Laser received his MS in electrical engineering from the University of British Columbia. He worked as a wafer fab diffusion process engineer for five years before joining SVG Thermal Systems in 1996, where he has been involved in the advancement of new hardware and processes for SVG's thermal products.
Werner Rust received his MS in chemical engineering from the University of Berlin, Germany. He has more 20 years of semiconductor experience, starting at Fairchild Semiconductor in 1978, developing bipolar and MOS process technology. Currently, he serves as the director of marketing at Silicon Valley Group Inc.