Issue



In situ steam generation: A new rapid thermal oxidation technique


07/01/2000







Satheesh Kuppurao, Hyun Sung Joo, Gary Miner, Applied Materials Inc., Santa Clara, California

OVERVIEW

In situ steam generation is a new oxidation technology for single-wafer RTP. Its process parameters can be controlled very precisely, and it provides productivity benefits compared to dry oxidation and torch-based wet oxidation. Its suitability for ultra-thin gate oxidation and STI liner oxidation is demonstrated.

Silicon dioxide is the most widely used and studied material in the semiconductor industry [1-3]. In this article, we introduce a new rapid thermal oxidation process of silicon with a technique called in situ steam generation (ISSG). The ISSG process has shown significant improvement in process results for applications such as ultra-thin gate oxidation and shallow trench isolation (STI) liner oxidation, while offering productivity advantages over regular dry rapid thermal oxidation.

ISSG oxidation


Figure 1. ISSG process in RTP XEplus Centura reactor.
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Batch furnaces typically use an external pyrogenic torch to produce steam. In the external torch configuration, H2 and O2 are combusted at atmospheric pressure in proximity to a hot element or in a hot-wall chamber that ignites the reaction, producing gaseous H2O. The resulting steam is then introduced into the hot-wall furnace tube to oxidize the wafers.

In situ steam generation is a different method of generating steam. ISSG is a low-pressure process (typically below 20torr) wherein pre-mixed H2 and O2 are introduced to the process chamber directly, without pre-combustion. Figure 1 shows a cross section of a cold-wall single-wafer chamber where the ISSG process takes place. Process gases (pure H2 and O2) are mixed in a plenum and are then injected into the chamber, where they flow across a rotating wafer heated by tungsten-halogen lamps separated by a thin quartz window. The reaction between H2 and O2 occurs close to the wafer surface because the hot wafer acts as the ignition source. To ensure process safety, the process pressure is restricted to below 20torr.


Figure 2. ISSG oxidation rate versus pressure.
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Figure 2 shows the oxide thickness dependence on pressure during an ISSG process where the temperature, time, and hydrogen concentration are fixed at 1050°C, 60 sec, and 33% H2 (10slm H2, 20slm O2), respectively. Conventional dry or steam oxidation rates decrease monotonically with pressure. The ISSG process exhibits a rapid increase in oxidation rate at pressures below 20torr, however. The growth rate at 10torr is nearly twice that of atmospheric dry rapid thermal oxidation. The increase in growth rate below 20torr is observed regardless of the H2 concentration, although the magnitude of increase depends on the H2 concentration. This suggests a radically different oxidation mechanism from those normally observed with dry or wet oxidation (molecular O2 or H2O/OH).


Figure 3. ISSG oxidation rate for thicker oxides (>50Å).
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Modeling studies [4] show that the oxidation growth rate exhibits a strong correlation to the atomic oxygen (O radical) concentration and not to any other atomic or molecular species. The atomic oxygen concentration is also independent of the reactor volume and depends solely on pressure, temperature, and relative amount of hydrogen present in the chamber. This implies that the process is easily scalable to 300mm geometries without much process impact. The O-atom peak concentration is a trade-off between radical generation through molecular collisions that are a strong function of temperature and pressure, and recombination processes that are a strong function of pressure or flow rate in the chamber. Hence, the ISSG process exhibits strong dependence on process pressure and flow rate in the reactor in addition to temperature.

Examination of oxidation rate at varying temperatures (Fig. 3) suggests traditional diffusion-based oxidation kinetics (x2 = Bt). Even though the oxidation is caused by highly active atomic oxygen species, as the oxide thickness grows, the process becomes increasingly diffusion-dominated. The activation energy of the parabolic constant "B" was found to be 1.39eV, higher than that for conventional wet oxidation (Ea = 0.71eV). Hence the ISSG process is strongly temperature-dependent compared to atmospheric wet oxidation.

The rapid thermal processing (RTP) chamber used has a multipoint, closed-loop temperature control capability that rapidly adjusts spatial temperature distribution across the wafer to ensure good within-wafer uniformity. Generally, within-wafer uniformities and wafer-to-wafer repeatability well below 1% (1s) are demonstrated for both thin (<40Å) and thick (>100Å) oxides.

ISSG oxidation applications

Because ISSG oxidation behaves as any other thermal oxidation, it can be used for all thermal oxidation steps during device fabrication. ISSG is demonstrating distinct technical benefits for a few applications. The faster growth rate of ISSG oxidation improves productivity while offering thermal budget reduction. The wide range of temperatures and hydrogen concentrations allow controlled oxidation for any thickness of oxide. Some of the key applications where ISSG has demonstrated improved device quality are STI liner oxidation and gate oxidation.

STI liner oxidation

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Figure 4. a) Furnace oxidation process (1100°C, dry O2, 100Å pad oxide, 1500Å pad nitride, 3500Å trench) with a trench top-corner oxide thickness of 250Å and a trench bottom-corner thickness of 200Å. Faceting and nitride lifting can be seen. b) ISSG oxidation process (1050°C, 33% H2, 100Å pad oxide, 1500Å pad nitride, 3500Å trench) with a trench top-corner oxide thickness of 215Å and a trench bottom-corner thickness of 210Å.

STI technology has been increasingly adopted to enable efficient and scalable layout for advanced device generations beyond 0.25mm. One of the most important issues with STI is the control of the trench profile [5, 6]. Sharp corners create regions of high electric fields leading to unacceptable device leakage. Additionally, crystallographic defects arise due to stress during subsequent thermal processes. Although trench etch processes allow some degree of control over the trench profile, a good-quality thermal liner oxide is essential to provide top-corner rounding and conformal oxidation along the entire trench. High-temperature furnace oxidation can provide some rounding, but accompanying problems such as slip, faceting at the bottom corners of the trench, non-conformal liner oxide thickness, and poor throughput at high temperatures have proven to limit its usefulness. Due to the enhanced oxidation rate, however, ISSG exhibits conformal oxide growth on all sides of the trench and eliminates faceting, while offering a highly productive, slip-free oxidation performance. The highly oxidizing atmosphere of ISSG also oxidizes a portion of the nitride pad, thereby providing stress relief at the top of the trench.

The TEM cross sections in Figs. 4a and 4b show conformal oxidation along the side and bottom of the trench. Faceting is observed at the trench corner during high-temperature furnace oxidation. High-temperature furnace oxidation also shows lifting of the pad nitride (bird's beak formation), while the ISSG oxidation considerably minimizes this effect and thereby reduces stress in the wafer.

Ultra-thin gate dielectric formation


Figure 5. Time-to-breakdown (Tbd) under constant E-field stressing at 15 MV/cm for 30Å oxide [8].
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SiO2 is the most reliable and stable thin dielectric layer that can be formed on bare silicon surfaces. In the ultra-thin gate oxide regime (<30Å), however, fundamental problems such as direct tunneling leakage currents, boron penetration, oxide reliability, and mobility degradation cause significant challenges to device scaling [7]. Conventional furnace-based oxidation has been the workhorse of the industry, but does not address the above problems. Furnace oxidation is difficult to scale below 20Å thickness, and the lower temperatures used during oxidation degrade oxide quality. Furnaces also do not allow easy integration with other technologies required for ultra-thin gate dielectric formation (surface preparation, nitrogen doping, poly-Si deposition, etc.).


Figure 6. Gate leakage current comparing dry RTO to 2% and 5% ISSG RTO for 30Å oxide [8].
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The ISSG ultra-thin gate oxide process uses a lean (1-2%) H2 mixture in the gas stream to control the oxidation rate of silicon. ISSG oxides consistently demonstrate better reliability than comparable furnace-grown oxides, or those created by dry rapid thermal oxidation (RTO). Several independent measurements of charge-to-breakdown (Qbd) of 30-50Å oxides show a threefold or more improvement in intrinsic Qbd of ISSG-grown oxides over furnace-grown oxides. Although there is no straightforward explanation for this improvement, a higher-quality oxide is probably formed due to the presence of oxygen radicals.

Etch rate studies on ISSG-grown oxides always show a lower etch rate than furnace-grown or dry RTO oxides, confirming a different chemical structure between ISSG and other oxides. In general, higher H2 concentrations reduce the etch rate of the oxide.

Additional experiments also demonstrate reduced leakage of ISSG-grown oxides in comparison to dry oxides and batch furnace oxides. Figure 5 shows improvement of more than seven times in time-to-breakdown (Tbd) measurements with constant field stress, and Fig. 6 shows improvement in gate leakage of 10 times compared to dry rapid thermal oxides, which were comparable to batch furnace oxides [8].


Figure 7. Ultra-thin ISSG oxide repeatability.
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Consistent improvement in oxide reliability (roughly an order of magnitude) has been demonstrated in multiple tests comparing ISSG with furnace dry and wet oxides as well as RTP dry oxides.

This reliable and repeatable ultra-thin ISSG oxidation process has been shown to grow SiO2 on silicon down to 10Å with excellent thickness uniformity across the wafer (thickness range <0.5Å). Figure 7 shows the repeatability of ultra-thin ISSG oxide grown at 950°C, using 1% H2 concentration diluted with nitrogen flow. Mean thickness of the oxide is 16.72Å, with a standard deviation of 0.15Å. Such thin oxides form the basis of advanced interface engineering required for ultra-thin gate dielectric formation. A promising technology for 0.13mm and smaller generations involves growth of thin ISSG oxide (<20Å), followed by nitridation of the top surface of the oxide with a remote plasma source — remote plasma nitridation (RPN) of gate oxide — to reduce effective oxide thickness.

Conclusion

In situ steam generation is an innovative oxidation technology developed for single-wafer RTP that offers significant advantages for critical oxidation applications for advanced devices. The ISSG oxidation process is influenced by parameters such as temperature, pressure, flow rates, and hydrogen concentration — all of which can be controlled precisely by modern equipment to offer excellent process control. ISSG offers significant productivity benefits over normal dry oxidation, is considerably simpler than external torch-based atmospheric wet oxidation, and is easily scalable to 300mm wafer-size production.

Acknowledgments

The authors would like to thank the following people for contributions and useful discussions during development of the ISSG process. The Thermal Process & Gate Division technology group consisting of Yashraj Bhatnagar, Nathan D'Astici, Sita Kaluri, Norman Tam, Dave Lopes, and Kelly Truman was instrumental in development and implementation of this process on the RTP Centura platform. Prof. Robert Kee (Colorado School of Mines) and Ajit Balakrishna (Thermal Processing & Gate Division, Applied Materials) provided a theoretical framework through modeling of ISSG reactions and verification of oxidation mechanisms. Motorola APRDL enabled initial characterization of thin ISSG oxides' electrical performance, and NASA Ames Research Center provided facilities and technology for characterization of process safety parameters.

References

  1. E.A. Irene, Y. J. van der Meulen, "Silicon Oxidation Studies: Analysis of SiO2 Film Growth Data," J. Electrochem. Soc., Vol. 123 (9), 1976.
  2. E.A. Irene, R. Ghez, "Silicon Oxidation Studies: The Role of H2O,"
  3. Electrochem. Soc., Vol. 124, pp. 1757-1761, 1977.
  4. F.M. Ross et al., "Dynamic Observations of Interface Motion During the Oxidation of Silicon," Surface Science, Vol. 310, pp. 243-266, 1994.
  5. R.J. Kee et al., "The Influence of Pressure, Fluid-Flow, and Chemistry on the Flame-Based Oxidation of Silicon," 28th Intl. Symposium on Combustion, Edinburgh, Scotland, July 2000.
  6. A. Chatterjee et al., "A Study of Integration Issues in Shallow Trench Isolation for Deep Submicron CMOS Technologies," SPIE Vol. 2875, pp. 39-47, 1996.
  7. H. Watanabe et al., "Corner Rounded Shallow Trench Isolation Technology to Reduce the Stress-Induced Tunnel Oxide Leakage Current for Highly Reliable Flash Memories," IEDM Technical Digest, IEDM, 1996.
  8. G. Timp et al., "Progress Toward 10nm CMOS Devices," IEDM Technical Digest, IEDM, 1998.
  9. K.G. Reid et al., "Dilute Steam Rapid Thermal Oxidation for 30Å Gate Oxides," RTP Symposium, 195th Electrochemical Society Meeting, Seattle, WA, 1999.

Satheesh Kuppurao received his PhD in materials science from the University of Minnesota, and his BS from the Indian Institute of Technology, Bombay. In Applied Materials' RTP process technology group, he was involved in the development of various RTP applications such as implant and salicide anneals, and he led the ISSG oxidation program. He is currently the global product manager and strategic technologist for Applied Materials' RTP product line. Applied Materials Inc., 2727 Augustine Drive, M/S 0701, Santa Clara, CA 95054; ph 408/563-6296, email [email protected].

Hyun Sung Joo joined the Applied Materials RTP process technology group after receiving his BS, MS, and PhD from the School of Materials Science and Engineering at Seoul National University in Korea. Currently a senior process technologist at Applied Materials, he has been a senior research fellow at the Korea Advanced Institute of Science and Technology in Korea and at the California Institute of Technology in Pasadena. His research has focused on materials surfaces and thin film interface properties.

Gary Miner was one of the primary engineers at G-Squared Semiconductor who provided the technology for development of the Applied Materials RTP product. He received his BS and MS in electrical engineering from Stanford University and is currently the director of Gate Module Technology in the Thermal Processing & Gate Division at Applied Materials. He is responsible for enabling gate-dielectric technologies such as thin ISSG oxidation, RPN, and high-k gate materials.