Technology News
06/01/2000
Gas purification enables SiGe production
A nickel-based catalyst media is one option among many for gas purification in process chambers, and it has been shown recently to be especially effective for SiGe production. A nickel-based purification media removes several impurities according to the reactions in the table.
 |
The ability to remove oxygen-based impurities with no heating makes it suitable for SiGe processing. Lower temperatures are needed for SiGe deposition compared to typical Si processes (<700°C vs. ~1000°C), and at these lower temperatures, oxygen is soluble in SiGe. This requires a much lower level of oxygen in the atmosphere during processing to prevent detrimental quantities of oxygen from appearing in the SiGe. The nickel-based purifiers accomplish this.
 Figure 1. SIMS profile of multitemperature SiGe deposits without purification. (Courtesy: ASM America) |
Secondary ion mass spectroscopy (SIMS) profiles were taken of impurities in SiGe depositions performed at different temperatures. Figure 1, without nickel media purification, shows that the oxygen content is an order of magnitude higher than its background level if the SiGe is deposited below 750°C. Figure 2, with nickel media purification, shows that the oxygen level is brought to the background level of the measurement technique at a processing temperature as low as 650°C. This creates a much more favorable process window for SiGe deposition with the purity required.
 Figure 2. SIMS profile of multitemperature SiGe deposits with purification. (Courtesy: ASM America.) |
These studies were presented by Dan Alvarez, director of technology development at Aeronex Inc., at the Compound Semiconductor Outlook 2000 conference in March in San Francisco, CA. Jeff Spiegelman, president of Aeronex, used this information to point out the need for new standards for gas purity for SiGe processing. He also stated that new standards are likely to be needed for SOI processing. According to Spiegelman, manufacturers of SOI wafers — not just compound semiconductor manufacturers — are very interested in this gas purification technology. It is believable that removing oxygen-based impurities from an SOI process is beneficial, but Spiegelman said that these companies have not revealed exactly what their process studies show.
Gate oxide breakdown mechanisms detailed, some cause for optimism
The increasing body of evidence in the critical area of gate oxide breakdown is altering the accepted view of the mechanism of oxide failures. Several teams of researchers presented their latest work at the IEEE 38th Annual International Reliability Physics Symposium in San Jose, CA, and much of the independent work points to the same set of conclusions.
The prevailing model describing gate breakdown had been the "E-field model," in which the strength and duration of the electric field across the gate are responsible for failures. One of the problems with this theory (and the driving force for much research) has been the "polarity gap," where experiments show that thin (<5nm) oxide film breakdown depends on the sign of the electric field. This model does not account for that.
The competing view has been a model in which the breakdown is driven by the voltage, not the electric field. Paul Nicollian of Texas Instruments Silicon Technology Development, Dallas, TX, presented strong evidence for this and demonstrated that the E-field model is physically incorrect. Breakdown is a result of the maximum — not the average — electron energy at the anode, so the voltage instead of the electric field is the key parameter. Jonathan McKenna of IBM, Essex Junction, VT, provided another set of data supporting this finding, using experiments with different levels of doping in p+ polysilicon gates. The charge-to-breakdown (QBD), which is related to the voltage, is the physical parameter most closely correlated to breakdown, not the time-to-breakdown (TBD) as suggested by the E-field model.
Another clarified area was the physical mechanism causing oxide breakdown. The two main theories that have been proposed are hydrogen release and anode hole injection. Hydrogen release is the process by which energetic electrons break Si:H bonds at interfaces, thus weakening the oxide. With anode hole injection, tunneling electrons release energy when entering the anode and create energetic holes that get injected in the gate oxide and cause breakdown.
Nicollian of TI presented some other work demonstrating that anode hole injection is likely to be the significant mechanism. He showed that bulk traps in the oxide, not interface traps, are responsible for breakdown. This was done by measuring stress-induced leakage current (SILC), in which tunneling through bulk traps is independent of the sense voltage, but tunneling through interface traps does depend strongly on the sense voltage. He also showed that anode hole injection increases the generation rate of bulk but not interface traps, so this supports anode hole injection over hydrogen release as the primary mechanism. Nicollian did say, though, that there are effects that are not addressed by anode hole injection, so more needs to be understood. He also pointed out that the relative importance of bulk and interface traps could change as oxide thickness is scaled.
Muhammad Alam of Lucent Bell Labs, Murray Hill, NJ, whose work also confirmed that oxide breakdown is voltage driven, used an improved anode hole injection model to explain many of the issues, and his results provided an optimistic view. The improved models match the existing data better than previous models, and when these are extrapolated to ultrathin oxides (1.5-2nm), the results show these films to withstand higher voltages than the linear extrapolations of other models indicate. The key concept is that at lower voltages, tunneling electrons produce fewer holes, and since lifetime is inversely proportional to the hole tunneling current, thin oxides are more robust at lower voltages.
One clever experiment provided further evidence against the hydrogen release mechanism. Jie Wu and his co-workers at the University of Illinois, Urbana-Champaign, IL, and Advanced Micro Devices, Sunnyvale, CA, knew that the lifetime of transistors was increased by a deuterium annealing step. If the hydrogen release model were correct, then performing that step with a hydrogen annealing step instead, thus replacing the Si:D bonds with Si:H bonds, would decrease the gate oxide reliability. No such effect was found, though, indicating that the hydrogen release model does not describe the mechanism.
Industry Roadmap likely to be overtaken
The engineers who face difficult silicon hurdles every day recently heard an optimistic view of the future. At the IEEE's 38th annual International Reliability Physics Symposium, in San Jose, CA, in April, keynote speaker Tak Ning said that we will find solutions to the many brick walls on the industry roadmap by thinking "beyond CMOS scaling."
Ning, an IBM fellow who focuses on silicon technology trends, discussed these challenges and some solutions in his talk "Silicon Technology Directions in the New Millennium." The industry is correct in fearing that some fundamental limits are being approached, according to Ning. He named gate oxide thickness, channel length and tolerance, threshold voltage or off-current, and reliability as some of the areas where solutions are needed sooner rather than later. He also saw the industry focusing on the many "technology opportunities" that will solve some of the problems.
Ning expects system-level integration (on-chip or on-package), integration of microprocessors and DRAMs, SiGe bipolar and BiCMOS devices, SOI, and advanced cooling technologies to lead the way. When asked if designers and customers were really ready for liquid cooling and other difficult technologies in a mainstream system, Ning turned the challenge over to packaging engineers to make such systems indistinguishable from current systems. He also said that the cost of SOI would be "worth it" shortly, making an analogy to CMOS, which was initially seen as being too expensive because of the extra masks. The advantages of CMOS quickly became "worth it." Similarly, it is cost, not physics, that is the pacing item for advances beyond 193nm in lithography.
Ning did admit that the art of silicon roadmapping is much more difficult than it used to be — you can't just draw a straight line on semi-log paper anymore — but he does believe that industry roadmaps are inherently self-nullifying. If everyone knows the targets for a given year, there will be plenty of people whose goal is to beat them, and it's more than likely that someone will succeed. The typical acceleration of roadmaps over the years is evidence of this and Ning believes that the roadblocks on the latest roadmap are not enough to stifle this trend. — J.D.
Patterned phosphors enable electroluminescent display
A new capability to pattern the phosphors in an electroluminescent (EL) display has resulted in the highest luminance yet for this type of display. iFire Inc. (formerly Westaim Advanced Display Technologies) made this breakthrough that gives a boost to this lesser known display technology.
 Figure 2. Construction of a hybrid thin-film/thick-film EL display. (Courtesy of iFire Inc.) |
In an EL display, an electric field is created across a semiconducting phosphor, and at a threshold level, the material becomes a conductor. The electrons flowing through the material when this happens excite luminance centers that produce light at a wavelength determined by the material and the doping. The display uses two phosphor materials, cerium-doped strontium sulfide (SrS:Ce) and manganese-doped zinc sulfide (ZnS:Mn). SrS:Ce, a cyan phosphor, was first developed in 1997 by iFire and is deposited by e-beam evaporation. This was an important step for full-color EL displays. ZnS:Mn, a yellow emitter, is a more widely known material that is very bright and can be filtered to provide a sufficient amount of red or green light.
Figures 1a and 1b show the previous and new structure of this display. By patterning the phosphors, the wavelengths of emitted light can be aligned with the blue, red, and green filters (Fig. 1b). This avoids some drawbacks of the old structure. The patterned phosphors allow for a much more efficient display because less of the light is being filtered out.
Also, in the old structure, yellow light being produced by the ZnS:Mn reduced the saturation level of the blue pixels because some of the green in the ZnS passed through the blue filter. Eliminating this effect enhances the appearance of the blue light. The phosphor layers can also be thicker when the layers are not stacked, and this allows more luminance centers/unit area, which increases the brightness of the display.
The luminance resulting from these developments is approximately 150cd/m2, which was demonstrated on an 8.5'' QVGA (320x240) display. This luminance is similar to a new 36'' CRT television — large flat TVs are among the target applications for the EL display — and it compares favorably with a 42'' VGA plasma display (120cd/m2), a 15'' LCD desktop monitor (95cd/m2), and a typical notebook screen (68cd/m2). iFire also recently demonstrated a prototype 17'' EL display with a luminance of 100cd/m2.
These EL displays are manufactured with a combination of thick-film and thin-film processes (Fig. 2). The substrate is a rigid opaque material, which makes it more robust and potentially higher yielding than an LCD built on borosilicate glass. The main thin-film stack consists of three layers: a thin-film dielectric layer and two phosphor layers.
The thin-film dielectric layer provides symmetry to the phosphor layers by creating an MISIM (metal-insulator-semiconductor-insulator-metal) structure. With this symmetry, there are equal numbers of electrons in the interface states at both sides of the phosphors. This ensures that voltage pulses at the same level produce the same amount of mobile electrons and therefore the same amount of light in both operating polarities of the AC-driven pixels.
A large area television would benefit from the relatively low cost of this process, while an application such as an automotive display would take advantage of its rugged nature. The latter application is the target of a manufacturing agreement between iFire and TDK, which was chosen because of its expertise in thick-film capacitors and other products where technology is similar to the relatively "low-tech" manufacturing of EL displays.
UL to unveil fire standard for plastics
More than two years after insurance conglomerate FM Global (formerly Factory Mutual) introduced the controversial FM4910 flammability testing protocol, Underwriters Laboratories, Northbrook, IL, was recently supposed to unveil an alternative test standard for fire-safe plastics in the fab.
If all went smoothly, UL's standard, known as UL2360, would have become effective on May 10 following a 30-day comment period, said Bob Backstrom, UL's engineering team leader, noting, "We were invited to participate in this by the industry." The goal of UL2360 was to offer a less expensive and repeatable test that would offer the same end-result of FM4910. That is, it would evaluate the combustibility of commonly used plastics in the fab, particularly those used for wet bench construction. UL2360 utilizes a cone calorimeter — a commonly used bench-scale tool for evaluating the reaction of a given material to fire.
Backstrom notes that UL2360 offers a hierarchical classification of material performance in fire propagation (i.e., Class 1, 2, or 3), rather than a pass/fail classification. Factory Mutual Research, the property loss engineering arm of FM Global, developed the 4910 protocol in 1997 to measure a material's combustion, smoke, and corrosion properties; the corrosion index was dropped last year after the organization found the corrosion test was unrepeatable.
To date, FM Global has approved 19 plastics from five suppliers. The introduction of FM4910 followed increasing concerns over extensive fab losses due to fires originating in wet benches and other tools made of the commonly used plastics such as polypropylene, fire retardant polypropylene, and PVC. The push for inherently fire-safe plastics has led to the introduction of new fire-safe materials, such as PVDF, a copolymer of vinylidene-fluoride and hexafluoropolypropylene, and CPVC, chlorinated polyvinlychloride.
Officials from FM Global say there is good correlation between FM4910 and UL2360 in determining fire safety for those materials that have either low or very high fire propagation properties, said Paul Higgins, engineering manager for the technology global practice at FM Global. "There are some areas in the middle ground .... materials that may not pass 4910 but might get a UL rating," added Higgins. "Then it's up to the end user to do a risk assessment to determine whether they should put in a firesuppression [system]."
Motorola's SiGe:C process targets wireless
Motorola Semiconductor Products Sector has successfully integrated a 0.35mm silicon germanium carbon (SiGe:C) process module into its high performance BiCMOS process technology platform (see figure). Technologists there claim this is one of the most cost-effective technologies for wireless ICs.
This is the first output of the joint work between Motorola's DigitalDNA Laboratories technology team and the Innovations for High Performance Microelectronics (IHP), formerly known as Institute for Semiconductor Physics. Motorola entered into a relationship with IHP Microelectronics in Frankfurt, Germany, in June 1999 to develop a wireless platform based on Motorola's CMOS and IHP's proprietary SiGe:C technologies.
IHP, a member of the Leibniz Society, is a team of 180 research and development professionals that offers innovations for high performance microelectronics with core competencies in process technology, circuit design, and systems. The IHP team develops solutions for wireless and broadband communications, networking, and multimedia markets.
Horacio Mendez, director of RF/IF device development for Motorola, says, "The wireless market will continue to demand highly integrated technologies with performance characteristics far beyond today's capabilities. In the future as wireless operating frequencies increase and we begin to integrate more passive components, the industry will require a more aggressive analog technology. That is why we have developed SiGe:C technology that allows straightforward integration and is portable to our next-generation high performance CMOS technologies."
Motorola has demonstrated integrated heterojunction bipolar transistors (HBTs) in their RF BiCMOS flow, with performance of 50GHz ft and 90GHz fmax, at half the current of traditional SiGe transistors. The addition of carbon provides better manufacturing latitude and a reduced noise figure. Motorola is able to achieve these performance characteristics with the addition of only one manufacturing step into a proven mainstream process. The result is a very cost-effective technology that lends itself to system-on-chip solutions, with substantial cost reductions for wireless applications such as radio architectures, and optimized system partitioning.
Behrooz Abdi, GM of Motorola's RF/IF Division, says, "Our RF BiCMOS technology is driven by Motorola RF/IF integrated circuit designers worldwide. This process hits the sweet spot of the cost-performance curve by integrating high quality active and passive devices, including inductors, with SiGe:C incorporated in a low cost CMOS platform."
Samples of SiGe:C RF circuits will be available for external evaluation by August, with the first product being a dual-band cellular low noise amplifier. Complete qualification of the SiGe:C technology is scheduled for the end of 2000, allowing production in early 2001. — P.B.
TI votes for AMAT's Black Diamond CVD low-k; IBM uses SILK
Despite IBM's recent approval of a spin-on low-k dielectric film from The Dow Chemical Company, the battle between spin-on and CVD low-k films remains heated following plans by Texas Instruments to use Applied Materials' Black Diamond low-k CVD film in its high-performance 0.13mm copper devices.
 Cross section of Motorola Semiconductor's SiGe:C HBT. |
In May, TI was scheduled to demonstrate 0.13mm copper devices using Applied's Black Diamond system. IBM said in April that it used Dow's SiLK dielectric film, a spin-on material, to produce 0.13mm copper devices. Both disclosures indicate that chipmakers are making advances in the integration of copper and low-k technologies. But taken together, the disclosures also indicate that it may be too soon to call a winner in the spin-on/CVD low-k debate, if there is to be one at all.
For its part, TI evaluated a number of other low-k films, including SiLK, Dow Corning's HSQ resin and Honeywell's Nanoglass material; through Sematech, TI evaluated Honeywell's HOSP and spin-on FLARE materials, Dow Chemical's BCB material, and Novellus' Coral, a CVD film.
Wilbert van den Hoek, Novellus executive VP of integration and advanced development, believes some chipmakers will adopt a parallel approach to low-k, perhaps using spin-on for high-performance devices and CVD for high-volume devices. "IBM, my guess, in the next six to 12 months will announce a CVD solution for copper/low-k," he said.
Van den Hoek believes a spin-on approach is more expensive than CVD, and expects IBM's foundry business will need to adopt a CVD approach to stay competitive with Asian foundries.
"I believe roughly 80% of our customer base will put an all-CVD low-k solution into production," he added, noting that the remaining 20% will lean toward spin-on low-k with four CVD thin films for diffusion barriers, etch stop, and a double layer hard mask. "We're engaged with all top 10 chipmakers."
At TI, plans call for the chipmaker to roll out the copper/low-k process first on its 0.13mm high-performance DSP and Sun Microsystems devices, while mainstream 0.13mm products will use copper plus fluorinated silicate glass (FSG). TI's mainstream high-volume devices will use the copper/Black Diamond low-k at the 0.10mm node.
Peter Rickert, TI ASP platform manager, said TI's copper/low-k device uses six levels of metal with four levels of Black Diamond, which has a dielectric constant of between 2.7 and 2.8. TI chose to go with a CVD film for several reasons. CVD is a known fab process, and TI had negative integration and outgassing experiences with spin-on materials in the past, Rickert said.
Production of copper with Black Diamond will begin at DMOS-6, TI's first 300mm fab, which is slated for qualification at the end of 3Q01. DMOS-6 also will house production of the copper/FSG mainstream devices, and Rickert noted that TI is contemplating rolling out a 0.18mm aluminum process at the 300mm fab.
SC300 finds DUV problems
Experiments at the Semiconductor300 fab in Dresden, Germany, have found that 300mm wafers are especially sensitive to backside defects when doing deep-ultraviolet (DUV) lithography.
The Dresden fab pilot line, jointly owned by Motorola and Infineon Technologies, includes five lithography clusters and a total of 110 process tools. The process team produced 990 64Mb DRAM chips on a 300mm wafer, 2.4x the 420 equivalent chips for a 200mm wafer. They used a 22mm x 33mm exposure field, and found that a DUV scanner gave better overlay than a stepper, according to Thorsten Schedel and others from SC300 in a report at the recent SPIE Microlithography conference.
Backside particles, however, caused lithography focus spot defects, and this led to a loss of pattern transfer and die yield. The particles do not come from the lithography itself, but from previous process steps, such as diffusion or CVD. Added backside cleaning steps could solve the problem, but this would add cost and processing complexity, said officials.
Another problem is the chuck design. A ring chuck had three to four times the contact area of a pin chuck with variable spaced contact points, and rework rates were typically twice as high with the ring.
Running the masks took 6.5 hours vs. 45 minutes for a 200mm wafer, more than eight times longer on a Sun workstation, suggesting that overlay corrections must be incorporated in OPC software to cut down the excessive runtime. — B.H.
Several targeting friendly cleaning replacements
Several leading semiconductor manufacturers in the US and Europe, including Philips, have teamed with FSI International to develop environmentally friendly wafer cleaning and resist stripping process technologies. This work is focusing on FSI's patented ozone-based DIO3 cleaning process as a means to reduce the use of harsh and more costly chemicals, such as the sulfuric-peroxide mixture or Piranha in photoresist stripping and RCA in cleaning (see figure).
Don Mitchell, president and CEO of FSI, notes, "Chemicals such as H2SO4, H2O2, and NH4OH require extensive neutralization at disposal, a very expensive process, especially in Europe where environmental disposal regulations are particularly stringent." According to Mitchell, reducing chemical usage not only provides positive environmental outcomes, but results in cost savings as well. "Manufacturers can expect savings in chemicals of $100,000/year in a fab with 20,000 wafer starts/month; this averages 4 to 6 cents/wafer in savings, depending on the process recipe being used," he says.
Philips has been using FSI's supersaturated DIO3 system since August 1999 in its Eindhoven research facility for front end of line (FEOL) and back end of line (BEOL) photoresist strip and FEOL critical cleaning. This R&D installation has been used to demonstrate to other Philips production fabs the cost saving of the DIO3 process. Through lower chemical and water usage, Philips expects to positively impact its COO and show a return on its investment in new cleaning equipment.
Working with another leading European semiconductor manufacturer where DIO3 is already used in production, FSI and the customer are developing "new recipes in the area of low-cost pre-diffusion cleaning."
In yet other work, a joint development program between International Sematech, AMD and FSI, DIO3 is being evaluated in AMD's Sunnyvale, CA, facility for FEOL resist cleanup. "This project is targeted to eliminate the use of Piranha from photoresist cleanup," said Phyllis Pei, International Sematech ESH program manager. "It is through joint development programs of this kind that our members become aware of processes that may result in environmental benefits." — P.B.
SOI wafers based on epitaxial technology
 |
The key to making epitaxial SOI wafers are: a hydrogen annealing step that creates an atomically flat surface, and a technique shown here using "water jet" technology for splitting off the bonded wafer without damage. Thus, seed wafers can be reused, making this an economically feasible process, according to two authors from Canon's ELTRAN Business Center. For more information, see "SOI wafers based on epitaxial technology," by Kiyofumi Sakaguchi and Takao Yonehara, located on p. 88.
Phase-shift masks challenge CDs
 (Figure courtesy of Surface/Interface) |
The emerging, limiting issues with optical and electron beam critical dimension (CD) metrology techniques — namely charging problems with scanning electron (SEM) technology; the need for 3D data and for real-time and nondestructive metrology; and unambiguous precision and accuracy — come together in a challenging way on phase-shift masks. The challenge is that multiple dimensions must be monitored and controlled. Many process-critical measurements are associated with quartz-on-quartz steps; the latter are too small for optical techniques and difficult with SEM because of charging. Also, z-dimension measurements are required from phase shift masks because these dimensions can change the phase of light uncontrollably. This illustration shows a Stylus NanoProfilometry (SNP) image of a phase-shift mask (insert) and a diagram of the various measurements of interest that can be taken simultaneously from each SNP scan line used to make up this image. Z-height measurements are clearly apparent. Collectively, these measurements define the structure in greater detail. — P.B.
Extrusion coating considered applicable to 300mm wafers
From early tests with a modified large-panel coater that showed extrusion coating could produce ±2-4% uniformities over a wide range of thicknesses on wafers, developers of this technique now see its potential for 300mm wafer processing and as an alternative to spin coating (see figure).
Extrusion coating directly applies photoresist, polyimide, and other polymers to a substrate without spinning and without significant material waste. The technique uses a precision extrusion die which is moved, at a close fixed distance (i.e., 75-150mm), linearly over a substrate. Simultaneously, the process fluid is metered through the die, forming a coating bead that ultimately deposits a thin uniform film onto the substrate. Precise control of a number of parameters is necessary to achieve the desired coating results.
Greg Gibson, chief technology officer at FAS Technologies, tells Solid State Technology that extrusion coating was initially developed for the flat panel display industry where it has been used for coating photoresist, color filter photoresist, and polyimide, primarily on large glass substrates. "Early production implementations of the technology combined the extrusion coat with a subsequent spin process to achieve final uniformity; further development eliminated the need for spinning and resulted in extrusion-only processes that could meet or exceed the coating results from the spin process," he says.
Primary advantages of the extrusion process include:
- significantly reduced material waste (polymer utilization is greater than 95%),
- ability to handle very large substrates,
- improved coating near edges (i.e., any edge-bead removal process is reduced or eliminated), and
- uniformity equal to or better than the existing spin coat methods.
Gibson adds, "In addition to application of relatively thin films needed for AMLCD production — 1-2 micron measured after softbake — the extrusion process has also been successful in coating 5-50 micron thick films used in the production of MCM/HDI."
After its initial process results, and with feedback from a number of end-users, FAS Technologies has developed an extrusion-coating-based wafer coating system. "One of our primary challenges was adapting extrusion, which is inherently a steady-state web process, to single substrate processing. In addition, we needed special fixturing techniques to coat round substrates and provisions for maintenance of the coating die and wafer edge treatment," says Gibson.
According to Gibson, extrusion coating on wafers offers a number of process advantages:
- A wide range of coating thicknesses can be applied with a single polymer formulation (e.g., 5-30mm from a typical high viscosity photoresist).
- Very thick layers (>100um depending on the polymer) can be applied in a single pass.
- The process offers excellent coverage over severe underlying topography.
- Spin-induced striations due to very large features are eliminated.
- The relatively low speed, low stress application of theprocess results in less stress compared to spin coating. (Studies are planned to characterize both the overall film stress and potential stress orientation differences.)
Gibson notes, "Although initial results indicate a tendency toward planarization, we have efforts underway to fully characterize the planar and conformal properties of this coating method versus other techniques."
 Extrusion coating applied Arch Chemical polyimide shows 13.248mm ±1.5% uniformity. |
A primary target application for extrusion coating is thick film on 300mm wafers; conventional spin coating often yields thicker areas in the center of the wafer and nonuniformity near the edge. Gibson says, "Concentrated on thick film coating, current best efforts yield better than ±3% uniformity to within 5mm of the wafer edge on both 200mm and 300mm wafers." Edge effects for extrusion coating are different than those for spin coating; they are due primarily to surface wetting and surface tension properties. "The as-coated wafer has full coverage to the perimeter, but does not exhibit any backside contamination from the coating material. This means that end users may be able to obtain more usable devices from each wafer," says Gibson. (If an uncoated edge is preferred, an innovative low-speed edge-bead removal can be effectively applied, even on very thick polyimide layers.)
The extrusion process is inherently efficient, in regard to polymer usage, as no material is spun off of the substrate. For square or rectangular substrates, the material utilization is greater than 95%. For round substrates, the geometry of the fixture reduces the utilization to about 75%. "Still, this is superior to conventional spin coat processes that may have utilizations as low as 10-20%," notes Gibson. "In addition, solvent consumption is <5cc for a 200mm wafer, which contributes to cost of ownership reduction. Process efficiency and waste reduction are tremendous advantages for IC manufacturers faced with increased pressure to reduce the environmental impact of wafer fabrication."
Since the as-extruded film has full solvent concentration, the post coat handling and baking differs from conventional processes, where the wafer is typically dry or semi-dry after spinning. Baking in particular has additional challenges, particularly with polyimide coatings, where the slow evaporation rate of N-methyl-2-pyrrolidone combined with the full solvent concentration in the thick film can result in extended bake duration. Joint development, for both the coat and bake process, is underway with end users to optimize and refine the overall process for production applications.