Hot topics at MRS: low-k, dopant profiling, copper

06/01/2000

MRS REPORT
Part 1

Overflow audiences heard about the latest developments in semiconductor processing research at the Materials Research Society Spring Meeting in San Francisco at the end of April. Hot topics included characterization of low-k dielectrics, dopant profiling, new gate materials, and copper precursors.

Doping requirements

Ion implantation and dopant characterization are areas that seem especially driven by the new International Technology Roadmap for Semiconductors. Researchers discussed fundamental limits extensively in these sessions, but in an invited talk, Yuan Taur of IBM had the upbeat view that CMOS scaling can be taken down to 20nm with ion implantation. This will require plenty of work, however, with the key being a "SUPER-HALO" vertically and laterally optimized, nonuniform doping profile, as the next step beyond retrograde and halo profiles. The tools needed are ultrarapid thermal annealing for an abrupt lateral profile, as well as high-resolution 2-D dopant profiling capability to characterize the dopants. Taur also said that the importance of junction depth is overemphasized in certain cases. Once it is greater than the gate depletion width, the short channel effect is insensitive to junction depth. In fact, ultrashallow junctions can be detrimental if they make the sheet resistance too high.

H.J. Gossmann of Lucent Bell Labs did related studies to identify the limits of ion implantation and reached the conclusion that electrically active dopant concentrations beyond solid solubility limits are needed, and ion implantation has not demonstrated that so far. Like Taur of IBM, Gossmann emphasized the importance of steep lateral slopes, with 4-5nm/decade required very soon. The best seen so far is 8nm/decade.

One alternative to ion implantation was solid source diffusion (SSD), discussed by Sang-Hyun Oh of Lucent Bell Labs. Oh presented a new vertical MOSFET device, with a 50nm gate length. He claimed that it is the smallest device yet made with current production tools, and that it could be scaled down to 30nm. In the vertical structure, the gate is defined by film thickness, thus avoiding the challenges of scaling lithography to that node. SSD was used to create self-aligned source-drain extensions (SDE). PSG was deposited in the structure, and the P was driven in during a 5-sec RTA step at 1050°C. P doping was below the solid solubility limit, but the results were better with b doping, reaching 9nm/dec lateral abruptness, which is competitive with the best ion implantation techniques.

In the area of thermal processing for shallow junctions, Srinivasan Chakravarthi of Boston University presented some modeling results demonstrating the importance of controlling the ramp-down rate in rapid thermal processing. Since most of the junction motion occurs after the fast ramp-up, a high ramp-down rate is needed to minimize the junction depth.

2-D dopant profiling

The key to all of this process development is a high-resolution 2-D dopant profiling capability. Rafael Kleiman of Lucent Bell Labs discussed some of the subtleties of scanning capacitance microscopy (SCM), a tool that is being used for this. SCM is essentially an atomic force microscope (AFM) probe with a metal tip and a very sensitive capacitance measurement capability. The technique is still not mature, though, with simulation assistance needed to help understand how the tip itself perturbs the charges near junctions as the measurement is being taken. Because of this, it is not yet possible to get dopant profiles directly in all cases. Still, SCM is not at fundamental limits, with tip engineering being the current constraint.

A related technique discussed by Pierre Eyben of IMEC is scanning spreading resistance microscopy (SSRM), which is also a derivative of AFM. In this case, a conductive tip is used, a bias is applied, and the current is measured with a logarithmic amplifier. Eyben noted that this technique gives carrier not dopant profiles, which is what matters for the device, but does not tell the whole story of the process. Joe Kline of North Carolina State University found an interesting way to increase the lateral resolution of this technique. Typically a high force from the tip is needed to get through the damage layer on the surface, and this degrades the probe tip during the scanning process.

By doing a chemical etch on the top surface of the material being measured, the damage region is removed. This decreases the required force, keeping the tip in better shape during the measurement. It also increases the resolution.

High-k gate dielectric materials

Several researchers showed promising results for some high-k gate dielectric materials. ZrO₂ figured prominently in the discussions. Charles Perkins of Stanford University demonstrated that the leakage current in ZrO₂ was 107 times lower than in an SiO₂ layer with the same equivalent oxide thickness (15nm). The physical thickness of ZrO₂ was about 50nm, with a dielectric constant of 20-25. He used ZrO₂ films deposited by atomic layer CVD (ALCVD) and he showed that these films also had much better leakage performance than ZrO₂ deposited by reactive sputtering. The ALCVD process provides excellent uniformity across a wafer because of the self-limiting growth, but he did note that the quality of the film is a strong function of the surface preparation. In another talk, Eduard Cartier of IBM showed that the ZrO₂ cannot be deposited directly on "HF last" Si — a thin silicate is needed.

Another promising material for high-k gate dielectrics is TaOxNy, which was studied by Hyunsang Hwang of the Kwangju Institute of Science and Technology in Korea. It has a dielectric constant around 100 and slightly less leakage current than Ta2O5, although processing issues remain to be solved. It is difficult to etch, and the surface degrades at high temperatures.

Low-k /damascene Cu mechanical properties

The timely results on low-k dielectric materials and copper interconnects were noticeably focused on the mechanical integrity of the structures. Several groups showed results of various test structures and new characterization techniques.

A shear test structure with Cu dots on various dielectric and barrier layers was used by IMEC to identify the weak points in the stack-up. Filip Lanckman showed results indicating that a TaN barrier layer between low-k materials and Cu improves the strength, and that the interface between SiO₂ and low-k materials can be a problem. They evaluated Honeywell's FLARE and Dow Chemical's SiLK materials. E.O. Shaffer of Dow was on hand to present some of the company's results on SiLK, but his presentation focused on future porous versions of the material with k ~1.5.

Some detailed theoretical analysis of "open" films, in which the material is treated as a system of struts, and "closed" films, in which the material is treated as a continuous layer with isolated bubbles, provided an interesting framework for comparison. Shaffer argued that fracture toughness — the resistance to crack initiation — is the mechanical property of most interest, and he showed that SiLK would remain tougher than other low-k dielectrics, even with the porosity required to get k down below 2.0.

In a few of the more esoteric talks, some unusual techniques were used to look at the structure of porous low-k materials. Wen-li Wu of NIST showed how specular x-ray reflectivity in conjunction with small angle neutron scattering can be used to measure the porosity, pore shape, average pore size, and pore connectivity of low-k films.

M.R. Baklanov of the Institute of Semi-conductor Physics in Novosibirsk used ellipsometric porosimetry, a technique in which an adsorptive material is introduced into the porous material, to evaluate the film. He performed measurements with a porous version of SiLK and Dow Corning's porous XLK.

William Gray of Dow Corning presented some process optimization work in conjunction with IMEC on the use of trimethylsilane (3MS) as a precursor for low-k films. This is what is frequently used now for a:SiCO:H films with k in the range of 2.5-2.8. They showed that the dielectric constant is strongly influenced by the deposition temperature, and that conventional tools that typically use SiH4 are fully compatible with 3MS.

Copper electromigration is another phenomenon that was thoroughly studied with novel test structures. Hazara Rathore of IBM gave more details on IBM's copper strategy. Electromigration evaluations showed that electro-plated (EP) copper was at least an order of magnitude better than CVD or PVD Cu for electromigration MTTF, and this is why IBM chose EP for its Cu breakthroughs. The key difference in the material is grain size, with the EP process resulting in 4mm grains, while CVD and PVD gave 1mm grains. He also showed that surface diffusion dominates during Cu electromigration, which is different from Al interconnects.

An advanced copper precursor that is air-insensitive and contains no fluorine, achieving resistivities down to 2mW-cm for 40nm-thick CVD films, was reported by Rolf Claessen and co-workers at the New York State Center for Advanced Thin Film Technology at SUNY. The CVD process uses Cu(tmshd)2 as a metalorganic precursor and hydrogen as a reducing and carrier gas, where tmshd is sila-b-diketone 2,2,6,6-tetramethyl-2-sila-3,5-heptanedione, which appears to have wider intermolecular spacings than some alternate precursors.

Recrystallization of an electroplated copper film at room temperature can drive grain growth in sputtered Cu underlayers, producing large grains that can improve electromigration resistance, indicated M.E. Gross of Lucent Bell Labs. He discussed a new sidewall texture component in damascene copper samples, and reviewed how the texture of the refractory-metal diffusion barrier and the topography of the damascene structure can influence the texture of the plated Cu layer.

More reports from the Spring MRS show will appear in the next issue.

Jeff Demmin, Senior Technical Editor, Bob Haavind, Editor in Chief