CMP: Market trends and technology
06/01/2000
Lita Shon-Roy, Applied Marketing, Danville, California
The chemical mechanical planarization (CMP) market is one of the fastest growing technology areas within the semiconductor process sector. With equipment and materials revenues estimated at more than $1 billion in 1999, this combined market is slated to exceed $2.4 billion by 2005 (Fig. 1).
Equipment market
Over the past five years, the CMP equipment market has had an average growth rate of 36%/year, and is expected to total $900 million in sales revenues for 1999 (35% more than 1998 sales revenues; Fig. 2). In contrast, the entire equipment market has only grown 8% over the past five years, even though its sales revenues are much larger ($29 billion in 1999) than total CMP revenues. For the purposes of this report, the CMP equipment market includes CMP polishers with and without fully integrated cleaners, and excludes stand-alone post-CMP cleaners. "Fully integrated" means that the post-CMP cleaner is incorporated into the CMP tool platform, allowing wafers to be cleaned and dried before leaving it, i.e., "dry-in-dry-out." This is a relatively new feature for most CMP tools; a large portion of the CMP installed base does not have it. By 2005, however, CMP equipment revenues will be generated almost entirely from sales of CMP tools with integrated cleaners, a market that it is estimated will exceed $2 billion in that year.
 Figure 1. CMP equipment and materials revenues. |
Key players in the equipment market include Applied Materials with a 50% market share, Ebara with 25%, SpeedFam/IPEC with 15%, and Lam Research with 5%. Although Applied Materials is relatively new to CMP (its first CMP product, Mirra, was introduced in 1997), the company was able to capture a substantial part of the market in a very short time. By far the largest semiconductor process equipment company in the world, Applied Materials leveraged its capital resources with worldwide service and performance guarantees to win market share from former market leader SpeedFam/IPEC (originally Westech). Last year, Applied Materials furthered its CMP technology development by acquiring Obsidian, a small manufacturer of a CMP linear polishing tool targeted at copper and slurry-free applications.
IPEC and SpeedFam, at one time the number one and number two suppliers of CMP equipment, have been dwarfed by Applied Materials and Ebara. Ebara, second only to Applied Materials, has gained most of its market share from Asia; the company is the number one supplier in both Japan and Taiwan.
Although linear polishers are less commonly used in comparison to rotary polishers, Lam Research has been making headway with its tool, the Teres. Offered with a fully integrated cleaner, this tool has been gaining in popularity for shallow trench isolation (STI) CMP applications.
 Figure 2. CMP equipment market. |
As with other global product sectors, the CMP equipment market is highly dependent on service/support, as well as its own ability to provide innovative yet cost-effective solutions. As a result, small companies do not survive very long without being purchased by larger companies or merged with the competition. For example, IPEC and SpeedFam merged into one company last year, and OnTrak, a small cleaning equipment company (brush cleaning for post-CMP), was acquired by Lam Research in 1997. It is anticipated that this trend will continue as companies struggle to compete globally, cut costs, and keep up with technology.
Materials market
The CMP materials market includes slurry, pads, and carrier inserts. This market has grown, on average, 19%/year over the past five years, totaling $170 million in sales revenues for 1999 (an increase of 20% over 1998 sales revenues). The materials market is more stable than the equipment market: In an industry slowdown, though fabs may halt equipment purchases, they usually continue to buy materials to feed existing tools. The total materials market is expected to reach $450 million by 2005 (Fig. 3).
The slurry market alone reached $119 million in 1999. Cabot is its leader with a 52% share, followed by Rodel with 20%, EKC with 6%, and Fujimi with 5%. During the last few years, a number of new players have entered the race, including ACSI/ATMI, Bayer, DuPont, Nissan Chemical, and Wacker. The market for slurry is expected to reach $314 million by 2005.
Technologies being actively developed include slurries for copper CMP and low-k dielectric (k<2) CMP. A competing technology recently announced by Allied- Signal and SEZ also addresses the need for copper CMP, but removes the metal by spinning a liquid chemical onto the wafer.
At the end of 1999, the pad market was estimated at $50 million. Rodel is the leader with a 70% share, followed by Fujibo/Fujimi with 12%, and Freudenburg with 7%. The pad market is another arena that has attracted many new players. The newest is Cabot, which announced its entry into the pad market last year. It is anticipated that this growing market will be worth more than $133 million by 2005.
As in the equipment market, small companies cannot survive for very long in the materials market without somehow collaborating with would-be competitors. Joint development programs and alliances are becoming common. Rodel markets the Klebosol product, for example, a colloidal silica slurry made by Clariant; and AlliedSignal is in collaboration with SEZ to develop an alternative to copper CMP. Another method of survival is to go to the open market for capital. Cabot, for example, offered an IPO on 15% of its microelectronics materials business, which was completed last year.
 Figure 3. CMP materials market. |
Most of the CMP work to date has been concentrated in the US: More than 50% of all CMP equipment and materials, by revenue, is sold to US-based fabs. In other parts of the world, Japan, for example, has evidenced little activity in this area since the early 90s. The Japanese market, however, is still small, most likely due to the fact that most DRAMs have few layers of metal, as well as to the ultraconservative attitude of the Japanese toward process change. Interestingly enough, the Taiwanese fabs have been very active in CMP development over the last few years. Most of these fabs now claim to have ILD and W CMP production capability. In addition, two of the larger fabs, TSMC and UMC, have been involved in copper CMP development for almost a year. European fabs, on the other hand, although highly interested in CMP technology, have been much slower to adopt CMP processes.
Low-cost CMP technology
The main driver behind CMP is the promise of lower overall cost per function and/or cost per chip. Having the ability to increase functionality/square centimeter allows the manufacturer to sell chips at a higher average selling price without increasing the cost of silicon. In addition, the manufacturer can get a cost benefit from CMP by increasing the packing density of the device, resulting in more chips/wafer with minimal impact on process costs.
 Figure 4. W CMP process. |
CMP has therefore become widely accepted as the method that will enable chip manufacturers to build multilayer devices without compromising packing density. CMP processes are now commonly used for planarization of the interlayer dielectric (ILD) and tungsten (W) plugs (also referred to as a single damascene process; Fig. 4). It is also being used for creating metal traces in combination with plugs, referred to as a dual damascene process (Fig. 5).
As an enabling technology, CMP eliminates concerns regarding poor linewidth definition caused by lithography exposure over uneven topography, and allows for finer linewidth/pattern definition. For example, an uneven surface will result in poor exposure (poor depth of field) because of the high and low regions of the surface. The result is a wide variation in linewidth — some lines will be much wider than originally designed, while others may be so underexposed that they don't exist at all.
The damascene approach consists of etching the metal pattern into an oxide layer, and applying CMP after metal deposition. The metal etch step is entirely eliminated and the resulting topography will not hinder patterns of additional oxide/metal layers. Dual damascene is a method of creating two metal layers using just one metal deposition step (see Fig. 5).
To date, ILD (typically silicon dioxide) CMP and tungsten CMP are the most mature CMP processes; it is estimated that nearly 100% of all fabs running CMP processes are using both CMP ILD and W CMP. A small percentage of fabs (<20%) use CMP for STI formation and/or polysilicon gate definition. In addition, the majority of logic fabs are now active in the development of copper CMP processes.
CMP is currently being used by a few fabs to make logic devices (primarily microprocessors). These devices can benefit from CMP because of their relatively high number of interconnect layers (now up to 7). To a much lesser degree, CMP is being used to make memory devices. But devices such as DRAMs typically have three or fewer layers of interconnect and therefore get less benefit from CMP. Some DRAM suppliers, however, have found advantages to using CMP to help define the capacitor region of the device, i.e., trench capacitors. The use of CMP for memory devices is anticipated to grow as designs increase in density and number of metal layers.
Copper and CMP
In order to exploit the cost benefits of increased packing density on a chip, the number of metal interconnect layers needs to be increased. To accomplish this, a better metal than aluminum must be employed. As geometries shrink to <0.18mm, aluminum becomes a poor conductor and exhibits electromigration problems. After much research and development, copper has become accepted as the metal of choice for next-generation processes, since it allows higher switching speeds than either tungsten or aluminum, is a better conductor of electricity, and is more resistant to electromigration, providing an improvement in reliability for any given current density.
The desire to integrate copper into a chip has driven the need for more CMP development work, because copper is most easily patterned using CMP technology. Copper is inherently difficult to etch and the most effective method of patterning it is to etch the ILD first, then deposit copper and follow up with a CMP process to remove all metal except that which is left in the etched ILD traces (the damascene process; see Fig. 6).
Cost savings/wafer, using copper interconnect together with dual damascene technology, are estimated at 10-20% depending on the number of wiring layers. When combined with an increased wafer size, to 300mm, the total cost savings can be as high as 30-40%.
To date, copper is being used for low-level production (mostly pilot production) at a handful of companies. At the 200mm wafer size, copper interconnects have been incorporated into IBM's Power PC750 and PC740 microprocessors for use in Apple Power Macs and handheld devices; Motorola's PowerPCs for use in Apple computers; and TI's DSP chips. Mass production using copper at each of these other fabs is anticipated in mid- to late 2000.
In addition, AMD has announced that it will use copper for its AMD K-7 microprocessor, enabling it to achieve switching speeds of greater than 1GHz by the end of 2000. Finally, Intel appears to be running copper development in parallel with a 300mm effort. It will likely reach pilot production of wafers with copper by 2001, transferring the process onto 300mm wafers in 2002. Copper interconnect technology will be used for future versions of Intel's Pentium III, Pentium III Xeon, and Celeron, in addition to Intel's new IA-64 microprocessor.
All of the companies mentioned above are well along the copper and CMP learning curves. Also, a few of the foundry suppliers like TSMC and Winbond are already offering copper CMP processes. Most other companies, however, have just started their development of copper processes, because until now, their device roadmaps have not required the use of a better conductor than aluminum, and/or they have chosen to wait until the copper deposition and CMP processes have been debugged. Consequently, widespread adoption of copper CMP into the majority of fabs is not anticipated to occur until 2001 pilot production, with mass production to occur in mid-2002 through early 2003.
Obstacles to copper incorporation
Copper deposition, and the prevention of copper corrosion during CMP and post-CMP cleaning, are considered the most challenging process problems to date. Without these difficulties, the adoption of CMP processes into product lines would have been much simpler and faster. In order to deposit copper effectively into narrow features (<0.18µm), without excessive voiding, fill problems, or contamination from source chemicals, other methods besides physical vapor deposition (PVD) and CVD had to be found. Electroplating, born out of the board-plating industry, has been found to provide the most suitable film for copper CMP processes. Copper electroplating has the ability to fill narrow gaps completely with a high-purity copper film, although the process is quite complicated when applied to semiconductor devices.
The electroplating process must be customized for each set of device geometries. Variations in step heights, for example, make uniformity very difficult to achieve. In addition, seed layer adhesion problems and continuity problems add to uniformity and film deposition problems. A seed layer of copper must be present in order for copper to "plate-out" on the wafer surface.
 Figure 5. Dual damascene process flow II. |
One of the more difficult process challenges is the prevention of copper corrosion during and after CMP. Corrosion is typically caused during CMP by the slurry oxidizer, galvanic cell formation, and/or electrochemical reactions. Chemical oxidation, hence corrosion, can result from the interaction of the copper with the oxidizer in the CMP slurry. Galvanic corrosion results when two metals of different electrical potentials are in contact with an electrolytic solution (i.e., slurry or cleaning chemicals in contact with tantalum and copper). Similarly, electrochemical corrosion can occur when copper is in contact with both p- and n-doped silicon regions in an electrolytic solution, in the presence of light.
Other technical trends/obstacles
In addition to copper interconnects, technical trends related to CMP include low-k dielectrics; colloidal slurries used for metal CMP; slurry-free (fixed-abrasive) pads; linear CMP tools; and 300mm wafers.
Low-k dielectrics. In order to use copper for sub-0.18mm devices, a different intermetal dielectric solution must be employed to avoid the charge buildup that can occur within the ILD. Traditionally, silicon dioxide with a dielectric constant of k ~4 has been used for the ILD. For a device using multiple layers of copper, however, the dielectric layer should ideally have a k value closer to 2. Today, most work is still focused on copper deposition and CMP to minimize the number of process steps and maximize process control. At present, copper deposition/CMP development work is commonly combined with traditional plasma-enhanced chemical vapor deposition (PECVD) silicon dioxide, or at the very most, combined with a variation of PECVD oxide (i.e., SiOF with k >3.5 or SiOC, k >2.5).
Materials with dielectric constants <2.2 are typically porous and come with another set of unique processing problems. For example, most of these materials have problems withstanding the mechanical stresses applied by CMP and tend to delaminate from the wafer. In addition, consistency of the dielectric constant after deposition and stability of the precursors is not well determined. Once copper development work is complete, more effort will be focused on the low-k ILD.
Colloidal silica slurries. These slurries have been around for some time. They are starting to be used in greater frequency for metal CMP, however. Colloidal silica slurries have a smaller average particle size than either alumina or fumed silica (2-50nm), and tend to be less prone to agglomerate or precipitate than fumed. Fumed silica slurries consist of strands or groups of primary particles that can be as large as 100nm and have a greater tendency to agglomerate or fall out of suspension silicas, especially at low pH. Colloidal slurries typically exhibit lower defectivity and slower CMP removal rates, although they are more expensive to manufacture.
Most metal CMP processes have used some sort of fumed silica slurry to remove cosmetic defects after the first CMP process step (which typically uses an alumina-based slurry). More recently, colloidal silica slurries are being substituted into this second step and, in some cases, are being used for a single-step metal CMP process. This is particularly attractive because a one-step process should lead to better throughput. These specially designed colloidal slurries are often made with particles that are not true colloids, but which are kept highly suspended by a proprietary combination of chemistries. Others are truly colloidal, employing an acidic chemical medium (also proprietary) that helps to enhance metal CMP performance and removal rates.
Obstacles to the continued emergence of colloidal silica slurries as used for metal CMP mainly originate in device design. Device patterns that have a high density of metal patterning will tend to benefit more from a colloidal silica slurry process. As device density increases, the need for colloidal silicas will become more common. It follows that when copper CMP becomes better established, colloidal slurry processes will become more prevalent. Examples of slurries marked as having colloidal properties include Cabot's W2585 and Clariant's Klebosol, offered by Rodel, and Fujimi's Planerate 5000 or 6000.
Slurry-free processes. The cost of slurry can be overwhelming if left unchecked. Slurries today range in price from $15/gal on average to more than $30/gal for specialty copper CMP or STI slurries. At a usage rate of 150-200ml/wafer, the cost of running mass production (i.e., 5000-10,000 wafer starts/week) can be as much as $7,930-$15,860/week. Assuming $5-6/ wafer for CMP, it follows that the contribution to cost of ownership (CoO)/wafer can amount to more than 25% of the total CoO.
As a result, pad suppliers are starting to offer CMP pads that do not require slurry. Companies such as 3M offer slurry-free (also known as fixed-abrasive) pads that have the abrasives embedded in the wafer. In addition to the promise of cost savings, these pads have been reported as providing faster removal rates, up to 3x faster than conventional pads, and more repeatable planarity without having to condition the pad prior to the first run. At present, the main supplier of fixed-abrasive pads is 3M company.
Linear CMP tools. Linear polishing technology has been around about as long as rotary polishing technology. The physics of linear polishing dictate that every point on the wafer experiences the same pad velocity. Until recently, linear polishing tools have not been as popular as rotary-style tools, because they removed material too aggressively. Over the past few years, however, development work on linear CMP tools has tuned the process for CMP applications, and has also revealed important advantages in the polishing of STI structures and metal CMP. It has been reported that linear CMP effectively removes high spots with minimal material removal in lower regions, helping to minimize oxide and dishing. In addition, linear CMP tools have been shown to provide greater planarization efficiency, i.e., a thinner layer of oxide is required to planarize the wafer surface. (A thick layer of oxide is typically required to provide enough material to polish before planarity can be reached.)
Also in development is a continuous web format tool, a linear track CMP tool that has a fixed-abrasive pad fed from reel to reel. This particular configuration not only promises better planarization performance than conventional rotary style CMP, but also promises cost savings from not having to use slurry. This is especially attractive for copper and STI CMP processes, where slurry costs can be as much as $30-$40/gallon.
300mm. 300mm is often referred to as a technology trend unto itself, independent from CMP. It is being discussed here, however, because the timing of 300mm wafer production has been impacted by the advent of copper CMP. In the past, bigger wafers have been a way for fabs to add capacity, but today the current aim is to reduce chip fabrication costs. Although the cost savings from switching from 200mm to 300mm wafers are reported to be as high as 40%, the cost hit from having to invest in a new tool-set, pay for more expensive wafers (as high as 6 or 7x more than 200mm), has led many fabs to rethink their 300mm schedules. Current cost estimates of a 300mm fab range from $2-$4 billion. In addition, copper CMP has been identified as a technology that can help to reduce costs at the existing wafer size, further adding to the justification to delay 300mm process development.
Although 1999 was originally anticipated as the production year for 300mm, these cost concerns, in addition to the industry slowdown of 1997-1998, have pushed most pilot production schedules to 2002. The one exception is the Semiconductor300 fab in Dresden, Germany, a joint venture between Infineon Technologies (formerly Siemens' Semiconductor Group) and Motorola, and the first fab to ship product from 300mm wafers (in October of last year).
 Figure 6. IBM CMOS chip with copper interconnect. |
Coincidentally, mass production of copper is also expected for 2002. Starting production of a new process on an entirely new tool set geared for 300mm wafers is unlikely, however. Most fabs have chosen to delay 300mm production until their copper process is up and running. IBM, a fab that is at least 6-12 months ahead of other fabs in copper process development, is already producing chips with copper interconnect on 200mm wafers. They are expected to enter 300mm production with copper processes in 2002. Intel has also chosen to concentrate on copper first, expecting to hit production in late 2002 on 200mm wafers (with 0.13mm geometries) before moving to 300mm wafers. In addition, Motorola is already in pilot production of wafers with copper interconnect. Its experience at Semiconductor300 is sure to help Motorola speed up the incorporation of copper into the 300mm process.
In addition to putting copper interconnect development ahead of 300mm work, semiconductor companies have been able to delay 300mm costs by relying on semiconductor foundries. This trend is more and more prevalent today, where capital expenditures by foundries totaled $35 billion in 1999, a 20% increase over 1998.
Over the past several years, there has been a steady increase in foundry business and a decrease in fab-building activity. The continued increase in dependency on foundries may help to diminish large swings in semiconductor over/ under capacity. Ultimately, this may cause the five-year boom-bust cycle, typical of the semiconductor industry, to lengthen or to disappear altogether.
Acknowledgments
Many thanks to those companies that contributed information for this article, including 3M Corp., Applied Materials, Cabot, Conexant, Ebara, EKC, ICE Kanto, Lam Research, Lucent, Rodel, International Sematech, Silbond, SpeedFam/IPEC, Strasbaugh, Texas Instruments, VLSI Research, and Wacker. Pentium III is a registered trademark, and Pentium III Xeon and Celeron are trademarks of Intel.
Lita Shon-Roy received her BS in chemistry and her MS in electrical engineering, and has held marketing, sales, and process development positions. She is president of Applied Marketing, a consulting firm. This article is based on her book, CMP: Chemical Mechanical Planarization, published by ICE. Contact ICE at ph 480/515-9780, or the author at Applied Marketing, Danville, CA; ph/fax 925/855-8983, e-mail [email protected].