SOI wafers based on epitaxial technology
06/01/2000
overview
SOI wafers are gaining acceptance in the industry as the benefits they provide become more desired, and as the SOI suppliers increase capacity and reduce costs. The epitaxial SOI wafer process described here includes a hydrogen annealing process that creates an atomically smooth epitaxial layer, and a water jet splitting process that allows the reuse of the seed wafer.
 |
Kiyofumi Skaguchi, Takao Yonehara, ELTRAN Business Center, Canon Inc., Hiratsuka, Kanagawa, Japan
Silicon-on-insulator (SOI) wafers are widely known to provide benefits to device performance because of the isolation provided by the underlying insulator, as well as a higher quality of silicon in some cases. The SOI industry is still maturing, though, with many fabrication techniques still being pursued (see "SOI history — bursting through the gate with multiple options after many years," on page 92).
An epitaxial SOI process known as ELTRAN (Epitaxial Layer TRANsfer) provides the technical benefits of an epitaxial layer that is atomically smooth and free of crystal originated particles or pits, as well as the economic benefits of a reusable seed wafer. This technology is described here.
Fabrication of epitaxial SOI wafers
Figure 1 shows the process flow for the ELTRAN "SOI-Epi wafer." High-quality epitaxial layers are produced on porous Si layers formed on the surface of seed wafers. After the surface is oxidized, the seed wafers are bonded with handle Si wafers and split through the porous Si layers. The remaining porous Si layers are removed from the handle wafer side, and the handle wafers are made smooth by hydrogen annealing to produce the epitaxial SOI wafer. The split seed wafers are reclaimed and reused for the next seed wafers.
Active layer quality issues
 Figure 1. Epitaxial SOI wafer process flow. |
The quality of the active silicon layer is a function of the process used to create it. Figure 2 compares the characteristics of the epitaxial SOI wafer with those of the other SOI wafers, bulk, and epitaxial wafers now widely used in the Si process. When pulling crystals from molten Si using seed crystals, fine voids of 0.1-0.2mm, known as crystal originated particles or pits (COPs), are produced in bulk wafers. The structure is known to be a regular octahedron consisting of {111} faces lined with an oxide layer. Epitaxial wafers are free from COPs, however, because the particles or pits are not propagated to the epitaxial layers formed on the bulk wafers by vapor phase growth. This is the main reason that epitaxial wafers are now used not only in logic devices but in memory devices as well.
 Figure 2. Crystal originated particles or pits (COPs) in different types of wafers; epitaxial layers exclude them. |
Epitaxial wafers have also become popular as the device size approaches that of the COP, and COPs began to lower the reliability of the gate oxide films on bulk Si wafers. In the case of SOI, since the thickness of thin-film SOI has become equal to or less than the COP size, COPs produce Si-free voids in the SOI thin films. (This kind of defect is called an "HF defect" because it becomes apparent once HF infiltrates into it.) To produce 0.25mm technology MPUs or DRAM circuits at 99% yield, the HF defect density should be about £0.1/cm2. According to an estimate by Sematech, the progress of fine patterning requires the defect density to be reduced by a further order of magnitude. Thus, the technique of using epitaxial layers for the SOI layers will be useful for thin-film SOI devices because it effectively eliminates the COP issue. In addition to ELTRAN, new SOI processes are increasingly using epitaxial layers.
Film thickness control
An SOI layer formed by epitaxial growth features high controllability and flexibility of film thickness. In fact, thick-film SOI layers of several micron to ultrathin-film ones of £50nm can be fabricated by simply changing the growth conditions, rather than through special equipment or processes. Ultrathin SOI layers in particular require not only epitaxial layer thickness control but also hydrogen annealing to smooth the SOI surface without reducing the film thickness [1]. Other processes that reduce the surface roughness typically require the removal of significant material, thus reducing the thickness. Conventional polishing processes also lack the nm-level controllability and reproducibility as film thickness decreases. Therefore, a unique flattening method — by hydrogen annealing — was developed. This is a batch process in a diffusion furnace, and the process results in an atomically flat surface. The film thickness does not decrease by more than 1nm. The reproducibility and uniformity are much higher than those of the conventional polishing method.
 Water jet slices SOI layer from seed wafer. |
Taking advantage of the process flexibility, ELTRAN wafers have been used to make SOI MOSFETs with thin films down to 4nm [2] and channel lengths of £100nm, as well as micromachines based on thick-film SOI technologies. Since thermal oxidation occurred on the buried oxide (BOX) insulation layer, low defect density and high SOI/BOX interfacial quality were obtained. The BOX layer thickness can be controlled over a wide range, independently of the SOI layer thickness. The device application range is thus remarkably extended, as shown in Fig. 3. It may be possible to meet the needs of several devices with one SOI method.
Cost reduction
The possibility of seed wafer reuse and the splitting yield determine the degree of cost reduction possible for bonded SOI production. The splitting must produce cracking in a limited range of porous Si thickness and not damage the SOI layers or the seed wafers during propagation. Since the porous Si layers are a double-stacked structure with different porosities, the strain energy accumulated at the interfacial area limits splitting to an extremely narrow range [4-6]. The stress in the double-layered porous Si was evaluated by micro-Raman spectroscopy just before the splitting and by x-ray diffraction during the processes. Near the interface between the first and second porous Si layers, the largest negative Raman shift was observed where the porous Si was strained due to the difference of the porosities of the layers (Fig. 4). This was mechanically the weakest point in the structure. It is revealed from the x-ray rocking curve that the stress in each porous Si layer was dramatically reduced from 109dyn/cm2 to around 108dyn/cm2 by splitting, and that the difference between the stress in the two layers became quite small. This is due to the relaxation by the splitting. Therefore, the stress configuration induced by the double layers is responsible for the splitting mechanism.
For the splitting, a "water jet" technology was used. The water jet — a small collimated water stream — is injected at the edge of bonded pair and splits the two wafers at the thin porous Si layer. The double-layered porous Si structure contains the stress concentration, with the result that both of the split wafers (SOI and seed wafer) are covered by the porous Si protective layers. As Fig. 5 and the photos on p. 89 show, the water jet easily drives high-pressure water into narrow gaps by fluid wedging and applies uniform pressure, reducing the chance of damage. The splitting yield is over 90%, and automatic water jet splitting machines are already in production use [7].
 Figure 4. Raman shift depth profile just before the wafer is split. |
A critical part of a cost-effective SOI technology is the ability to recycle wafers. With this water jet splitting technique, it is possible to reclaim and reuse seed wafers. The quality was verified by comparing a third cycle of SOI wafers, fabricated with the same process as the first round, to the original set of wafers. HF defects, Secco defects, and light point defects (including the surface scratches) were measured <0.05/cm2, 4-8 x 102/cm2, and <50/wafer, respectively, for all generations of SOI wafer. Also, the RMS surface roughness was measured to be 0.10-0.12nm for all generations. These data show that no additional defects were introduced and that those qualities were not degraded at all through splitting and reproducing.
300mm SOI wafers
An epitaxial process avoids some of the challenge of processing 300mm wafers through the ability to process an entire wafer surface all at once. This has been shown with 300mm bulk epitaxial wafers, and it has been demonstrated with 300mm ELTRAN samples with a conventional grind and etchback process. Epitaxial growth equipment available in the market was used without changing the processes. The only unique machines required are the anodizer that produces the porous Si layer on the top of the starting seed wafers, and the water jet machine that splits the bonded pair at the porous Si layer. We have demonstrated 300mm epitaxial SOI wafers fabricated by the water jet splitting technology (Fig. 6.) The SOI thickness was approximately 150nm.
SOI market
 Figure 5. Wafer splitting by water jet. |
It is widely expected that SOI wafers, devices, processes, and design environments will be established in the near future to make SOI wafers as readily available as the current bulk wafers. Like bulk wafers (CZ, FZ, and MCZ), hydrogen-annealed CZ wafers, and epitaxial wafers, an optimal type will be selected from the current SOI wafer types according to the application. One likely source of cost reduction for epitaxial SOI wafer is the use of low-price wafers as starting materials. Also, like most other new products, once some device manufacturers begin using SOI wafers in large-scale manufacturing, it will become economically feasible for many companies to enter the arena with products and services that will further accelerate the acceptance. SOI design tools are one example.
High speed and low power will make SOI devices widely applicable, and there is no doubt that high-speed logic will first appear featuring the high speed and low power made possible by SOI. For widespread use in the CMOS world, the SOI quality must be equal to those of bulk and epitaxial wafers, and the price of SOI must be sufficiently low to encourage device development. At the same time, the price must reward the research and development efforts of SOI wafer manufactures and reduce the investment risk. In the past decade, SOI wafer quality and supply have greatly improved and are now sufficient for LSI processes. Now the burden is on the SOI providers to meet the needs of the market, so that the increasing demand can drive cost and prices down further. For example, to meet the growing demand, Canon is investing two billion yen in 2000 and is increasing its manufacturing capacity fivefold to reach 10,000 wafers/month. SOI capacity increases are also occurring at other companies.
Conclusion
Epitaxial SOI wafers are available today. The SOI uniformity is excellent, and the wide range of thickness possible makes this process an option for many types of devices. A key process is the hydrogen annealing step that creates an atomically flat surface. Also, a "water jet" technology is used to split wafers without damage, so that seed wafers can be reused, making this an economically feasible process. The process has been demonstrated successfully on 300mm wafers.
Acknowledgments
ELTRAN and SOI-EPI WAFER are trademarks of Canon.
References
- N. Sato, T. Yonehara, "Hydrogen Annealed Silicon-on-Insulator," Appl. Phys. Lett., Vol. 65, p. 1924, 1994.
- E. Suzuki, et al., "Highly Suppressed Threshold Voltage Roll-off Characteristics of the 4 nm-thick SOI N-MOSFETs in the 40-135nm Gate Length Regime," Proc. 9th Int. ECS SOI Symp., Vol. 99-3, pp. 260-265, 1999.
- Y. Arimoto, "Structure and Applications of SOI," Surface Science Tech., p. 447, 1996.
- K. Sakaguchi, et al., "ELTRAN by Splitting Porous Si Layers," Proc. 9th ECS SOI Symp., Vol. 99-3, p. 117, 1999.
- K. Ohmi, et al., "Water Jet Splitting of Thin Porous Si for ELTRAN," 1999 Int. Conf. Solid State Devices and Materials, p. 354, 1999.
- K. Sakaguchi, et al., "Water Jet Splitting in Stress-Controlled Porous Si," Proc. 1999 IEEE Int. SOI Conf., p. 110, 1999.
- K. Yanagita, et al., "An Application of the Water Jet for Splitting Bonded Wafers," Proc. Int. Symp. on New Applications of Water Jet Technology, WJTSJ, p. 137, 1999.
Kiyofumi Sakaguchi received his BE in electronics and communication engineering in 1988, and his ME degree in 1990, both from Waseda University in Tokyo. He joined Canon in 1990, where he has been engaged in the research and development of SOI materials, with a focus on thinning, splitting, and etching processes. He is currently a senior engineer of the ELTRAN Business Center.
Takao Yonehara received his BE and ME degrees in electronics in 1977 and 1979, respectively, and his PhD in electronics in 1986, from Waseda University in Tokyo. He joined Canon Research Laboratories in 1979, where he investigated hetero-epitaxy of silicon, laser annealing, and polycrystalline silicon films. He served as a visiting scientist at MIT starting in 1982, and when he returned to Canon in 1984, he became engaged in research and development of SOI fabrication techniques and applications. He is currently the deputy head of the ELTRAN Business Center, Canon Inc., 6770 Tamura, Hiratsuka, Kanagawa, 254-0013, Japan, ph +81/463-53-8839, fax +81/463-51-1054, e-mail [email protected].
SOI history — bursting through the gate with multiple options after many years
In 1998, IBM announced a breakthrough in manufacturing a high-performance, low-power CPU (Power PC with SOI wafers.) The SOI CPU delivers 30% faster performance and two-thirds lower power than a bulk-Si CPU. This achievement, with mass production to start this year, marked a turning point in the 30-year history of SOI research and development.
Following IBM's lead, other manufacturers announced their own SOI chip production projects, such as Seiko Epson's low-voltage SOI-IC driven by spring power for watches, Oki Electric's logic, Samsung Electronics' SOI-ALPHA, and the development project for mW-class ultra-low power LSIs at Japan's New Energy and Industrial Technology Development Organization (NEDO). These SOI CMOS chips are being rushed toward production, while dormant SOI technologies, especially thin-film SOI CMOS, are about to enter the practical stage. In addition, thick-film SOI bipolar, BiCMOS, and applications in the MEMS arena are showing steady progress.
The history of SOI development can be divided into three phases. The first was in the 1960s, when the SOI structure was created for the first time using silicon-on-sapphire (SOS), and a microprocessor was developed with it. The second phase occurred around 1980, when various methods of forming the SOI structure on a Si wafer were proposed. SIMOX (Separation by IMplantation of OXygen) was born, and the SRAM was developed as a radiation-hard device in this phase. The third phase started in the mid-1980s, when bond-and-etchback SOIs (BESOI) were developed, and it continues to the present day.
All of these SOI approaches are still under development — SOS, SIMOX, and BESOIs — with the specific technologies PACE, ELTRAN [1-3], and UNIBOND being added to the mix as well. These six techniques are now available for commercial use. Thin-film SOI wafers suitable for CMOS applications are limited to three techniques because of the quality requirements: ELTRAN (based on epitaxial technology), and the ion implantation approaches of SIMOX and UNIBOND. SIMOX is now being made by four manufacturers after 20 years of research and enhancements, such as dose reduction and ultrahigh-temperature oxidization. In the mid-1980s, direct bonding technology was announced by Toshiba and IBM, paving the way for BESOIs. This technology first attracted attention for its high crystal quality, but since the bonding technology had the drawback of etching from a bulk silicon wafer, new thin-film technologies were pursued. The result was IBM's double-etching method, Hughes's PACE, Canon's ELTRAN, and LETI's UNIBOND, all developed independently at about the same time.
References
- http://www.canon.com/eltran
- T. Yonehara, K. Sakaguchi, N. Sato, "Epitaxial Layer Transfer by Bond and Etch Back of Porous Si," Appl. Phys. Lett., Vol. 64, p. 2108, 1994.
- T. Yonehara, "ELTRAN SOI-Epi Wafer and SCLIPS by Epitaxial Layer Transfer from Porous Si," 2nd Int. Conf. Porous Semiconductors Science and Technology, p. 14, 2000.