Wafer Cleaning: Cu contamination control for advancedinterconnect manufacturing
05/01/2000
OVERVIEW
As IC manufacturers are moving to copper metallization for their most advanced products, contamination control presents a big challenge for the back-end-of-line manufacturing processes. Copper contamination could be introduced or spread from various sources, such as copper processing tools or wafers with open copper surfaces, and might cause catastrophic effects on production. By looking into a generic copper damascene process flow, requirements for critical cleaning steps can be identified, especially for fabs with mixed conventional aluminum and copper metallization.
Dieter Dornisch, Guangming Li, Maureen Brongo, Conexant Systems Inc., Newport Beach, California
With the implementation of copper (Cu) in advanced microelectronic interconnect manufacturing, a complex of new contamination control challenges emerges on various levels. These include control of Cu contamination within each wafer at the device level and control of Cu cross-contamination from wafer to wafer by the redistribution of Cu-containing particles during wafer processing or transfer. These concerns are especially critical for wafers in the front-end-of-line (FEOL) processing stage and for non-Cu wafers with traditional aluminum interconnects.
Many companies have chosen to deal with the fab cross-contamination concerns by building separate cleanroom facilities for the processing of Cu wafers. However, manufacturing economics favor the integration of Cu processing with aluminum manufacturing lines for many fabs.
 Figure 1. Post Cu CMP clean challenges: to remove CMP residues including slurry particles, Cu ions and other contaminants without causing dielectric and metal loss. |
On a smaller scale within each individual die, Cu must be prevented from migrating to the electrically active silicon regions or into dielectric films in order to prevent poisoning of transistors or degradation of the insulating layers (see "Effects of Cu contamination," page 140). Manufacturing process flows must therefore include multiple diffusion barriers to encapsulate fully the embedded Cu features on the wafer frontside and additional barriers to seal the backside and wafer bevel.
New cleaning steps, such as backside and bevel cleaning at certain critical stages, must be used in combination with these barriers to prevent the spreading of Cu-containing particles from wafers with exposed Cu to non-Cu wafers. This is especially critical if the two types of wafers share the same cleanroom area and potentially some of the same processing tools.
Containment strategies for Cu
As discussed in earlier papers, embedded Cu features can be built in a variety of single or dual damascene processing schemes [1]. They can be characterized by the sequence of lithography and etch steps for trench, via, and (if applicable) top or embedded hard mask patterning, and by the use or non-use of etch stop layers. In the completed device and during many stages of the manufacturing process, the embedded Cu lines and vias are fully encapsulated with barrier layers to prevent Cu out-diffusion into the surrounding dielectric and silicon areas.
 Figure 2. Optical micrograph of a patterned Cu wafer showing a clean surface with no corrosion post Cu CMP cleaning. |
In several process steps, however—e.g., those from Cu deposition to Cu CMP or in certain stages of the damascene etch and post-etch clean—Cu is exposed or present outside these boundaries. To prevent contamination and migration of Cu to deeper layers during these stages, the wafer must be fully sealed by a continuous diffusion barrier, and appropriate cleaning processes must be used.
The most obvious risk of Cu contamination occurs when large open areas of Cu are present on the wafer or when Cu-containing chemicals or waste by-products—such as electroplating solutions or Cu CMP waste slurry—are applied or generated. Another critical mode of Cu contamination results from the high-energy ion bombardment of exposed Cu surfaces during steps involving plasma processing, e.g., via open etch, ash, dry strip, etc. [2]. In an admittedly arguable order, the following steps can be considered to carry the highest risk of spreading Cu contamination, either into the deeper layers of an individual wafer or from wafer to wafer:
- Cu CMP,
- Cu deposition (including PVD or CVD seed layer deposition and electroplating),
- post-plating anneal,
- cap layer deposition, and
- damascene (via opening) etch.
In the following sections, we discuss specific cleaning requirements and barrier-related integration solutions for the prevention of Cu contamination during several of these critical steps and for wafer backside and bevel cleaning.
Copper seed layer deposition, electroplating, post-plating anneal
During Cu seed layer deposition, electroplating, and post-plating anneal, the wafer surface is almost completely covered with a blanket Cu film and fully exposed. Cleaning of the wafer backside and bevel at certain critical steps during this stage may be necessary to prevent the spread of Cu particles from wafer to wafer by way of wafer-handling equipment. A barrier layer needs to extend over the whole wafer front-side beneath the copper, around the bevel, and on the backside to prevent Cu from diffusing into the wafer.
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To prevent possible generation and redeposition of Cu particles from the wafer edge during wafer transfer, it is preferable to maintain a sufficient edge exclusion of the Cu seed layer or electroplated film. This must, however, be balanced with requirements for subsequent plating and CMP steps and the overall usable real estate on the wafer. Depending on die size, the loss in the number of product die on a 200mm wafer can be in the order of 10% when the edge exclusion is increased from 2mm to 5mm.
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Figure 3. Comparison of electrical performance: a) leakage current, and b) capacitance—of a low-k Cu structure with (POR) and without (DIW) a chemical clean.
Typically a full-face seed layer film is required to provide sufficient electrical contact close to the wafer edge to allow electroplating with <4mm edge exclusion. One potential way to prevent cross-contamination by Cu flakes from the edge of a wafer with a full-face seed layer is to introduce dedicated wafer carriers, which are used only to transfer wafers from the seed layer tool to electroplating and to add an edge bead removal (EBR) style edge clean. With the latter step, the seed layer can be removed from the wafer edge and bevel after plating. This edge clean could be integrated onto the plating tool or be separate. The edge clean chemistry must effectively remove Cu without attacking the frontside and backside diffusion barrier films, even when the chemistry is applied multiple times over the course of a multilayer damascene processing sequence. Another important criterion is a well-defined border of the edge clean zone on the wafer frontside near the electroplated film. An irregular or uncontrolled edge clean zone can later result in corroded areas or can create defects inside the usable area of the plated Cu film.
Copper films deposited by electroplating typically require annealing at temperatures ranging from 100 to 350°C to accelerate uniform grain growth across the whole wafer and to achieve a desirable grain structure inside embedded features [3]. Considering that Cu is already very mobile at room temperature, these annealing steps during back-end-of-line processing significantly increase the risk of Cu migration.
As discussed earlier, a simple or composite barrier film must shield the active devices and dielectric films across the whole wafer below the Cu film, around the edge, and on the backside to prevent diffusion of Cu into the wafer during this anneal step. On the wafer frontside, this function can be achieved with the trench and via liner barrier, which typically extends over the dielectric before being removed by CMP; this barrier also typically wraps around the wafer edge. At the bevel, the frontside barrier should overlap with a backside diffusion barrier film such as silicon nitride. One critical requirement for this backside barrier is that it be possible to clean it multiple times over multiple Cu metallization layers without its being completely consumed by the cleaning chemistry.
Cu CMP, post-Cu CMP cleaning
During Cu CMP, the excess amount of Cu on the wafer frontside is removed, together with the barrier film outside the embedded damascene features. Since CMP in general is a process where high loads of abrasive particles, in addition to possibly ionic or nonionic oxidizers and surfactants, are applied to the frontside of the wafers, it is important to have an effective clean. Various techniques of cascaded cleaning processes with or without mechanical brush scrubbing have been developed for this purpose. Double-sided brush scrubbing, for example, has become widely used.
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In the case of Cu CMP, however, the post-CMP clean bears the additional challenge of removing Cu completely from the dielectric surface. This task is further complicated by the close proximity to an effectively infinite Cu source (i.e., the embedded Cu damascene features; see Fig. 1). Any remaining Cu contamination on the dielectric areas would be permanently sealed into the wafer by the subsequent cap layer deposition and remain as a diffusion source and possible leakage path between the encapsulated damascene features. Cu contamination, typically found in ionic form absorbed on the surface of the dielectric layer, and a thin surface layer of the dielectric must therefore be removed without dissolving metallic Cu in the embedded features. Dissolved Cu would immediately re-contaminate the dielectric surface. After cleaning, the field has to stay clean until the dielectric cap—typically a few hundred Å of SiN or SiC—is applied. Also, any dissolution or chemical attack of the embedded metallic Cu during the clean would probably lead to corrosion defects and reliability concerns.
As shown in Table 1, satisfactory cleaning can be achieved using a double-sided scrubber with the vendor's proprietary cleaning chemical. Slurry residues were removed to the level of <10 adders at >0.25µm on oxide films with an oxide loss of <20Å/cleaning cycle, which is significantly less than the oxide loss during Cu CMP (in the range of 1000Å).
Copper contaminants from the CMP process can also be removed effectively from both frontside and backside. For oxide wafers polished with a Cu CMP slurry interchangeably with Cu blanket wafers, the Cu contamination level on the oxide surface at the frontside after post-CMP cleaning is <1 x 1010 atoms/cm2 as determined from TXRF (total reflective x-ray fluorescence) technique. While on DI water-rinsed wafers, the Cu surface concentration is 2.4 x 1012 atoms/cm2, more than two orders of magnitude higher.
The amount of Cu loss in the features during the post-CMP cleaning process is very small. In a static immersion test, a blanket copper film shows a Cu loss of only 2Å over one hour as determined by the inductively coupled plasma mass spectrometry (ICP MS) technique. In addition, no corrosion was observed on metal features after post-Cu CMP clean using one vendor's proprietary cleaning chemical (Fig. 2).
Post damascene via-opening etch clean
Via opening also creates new requirements for Cu cleaning. Copper sputtered during via opening reacts with the etch gases and resist residues and forms Cu complexes of various compositions on the Cu surface at via bottoms and on the sidewalls of the via and trench openings [4]. The composition of the etch residues depends on the etch processes and the materials involved. Silicon-based dielectric materials, including silicon oxide, silicon nitride, and carbon- or fluorine-doped silicon oxide, are commonly used as dielectric layers, etch hard mask, or etch stop layers. Typically they are etched in fluorine containing plasmas while carbon-based polymer dielectrics are etched in O2-based plasmas. Table 2 summarizes the possible etch residues involved in different dielectric etch processes.
These etch residues will most likely increase via contact resistance. They can also affect adhesion and step coverage of subsequent liner barrier layers and could cause serious integration problems, such as poor barrier integrity, discontinuous barriers, and metal delamination.
Due to the lack of volatile Cu compounds, a wet chemical clean or a dry clean combined with wet rinse is required for efficient Cu removal in the post-etch clean. Traditional post-etch clean solvents contain aggressive amine compounds that may cause Cu corrosion as well as degradation or absorption into low-k dielectrics. Less aggressive aqueous chemicals (i.e., slightly acidic or neutral) appear more compatible with Cu and low-k dielectrics, but satisfactory cleaning performance remains to be demonstrated.
Figure 3 shows boxplots comparing the electrical performance of a polymer based low-k and Cu structure with and without a chemical cleaning process for residue removal. After the dielectric etch process, wafers in group "POR" went through a chemical clean bath while the other wafers received DI water rinse only. All wafers were completed through Cu filling and CMP processing and were sent for electrical testing. The plot on the left shows that the POR chemical clean decreased leakage current more than 1000 times and had a much tighter distribution. In addition, the plot on the right shows that the intrametal-line capacitance remained the same for the POR-chemical cleaned wafers compared to those with only DI water rinse, though with much tighter control. This indicates that appropriate cleaning after etch to remove etch residue is critical in getting decent electrical yield as well as maintaining the low-k characteristics of the dielectrics.
Backside clean, film requirements
Copper contamination can arise from and spread through direct contact during wafer handling, as emphasized in several places during the previous discussion of the damascene process steps. Copper or Cu-contaminated particles from the wafer edge or backside can flake or be scratched off by wafer handlers or transport cassettes. From there the particles can easily be redeposited on other wafers. In Fig. 4, high levels of Cu backside contamination can be seen on metrology and processing tools that handle wafers with fully exposed Cu films.
 Figure 4. Measured wafer backside Cu contamination levels at various damascene process steps. |
A backside and edge cleaning step is necessary to remove Cu from the areas where the handler would make contact, in order to prevent cross-contamination of other wafers. This is mandatory before processing of Cu wafers on tools that could be shared with non-Cu wafers. Bevel and backside clean can be performed (e.g., on a single wafer spin etcher using wet chemicals) while protecting the wafer frontside with a N2 cushion on a Bernoulli chuck [5]. The cleaning process must be adapted to the nature of the backside film and the oxidation state of the Cu contaminants present. The barrier films on the backside and bevel in turn must be thick enough to allow the removal of Cu without being consumed before the wafers are completed through the line.
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Table 3 lists the Cu concentration measured by the vapor phase decomposition (VPD) ICP-MS technique on monitor wafers that were transferred face-down through a lithography stepper. The data show that the Cu level on control wafers that were processed prior to the processing of Cu wafers is the same as the Cu level on monitor wafers run after backside- and bevel-cleaned Cu wafers were run. It is evident that certain tools, (e.g., stepper and lithography tracks) can be shared between Cu and non-Cu wafers without causing cross-contamination if appropriate cleaning steps are implemented.
Conclusion
Despite the new contamination control and cleaning challenges Cu has introduced as a pure or primary interconnect material, a growing number of companies have shown that the associated risk is manageable and that copper manufacturing lines can be built in shared cleanroom facilities with aluminum interconnect manufacturing lines. New cleaning processes and chemistries working in combination with compatible barrier layers are essential for obtaining high performance levels of Cu interconnects with high manufacturing yields. Wafer bevel and backside cleaning is especially important to prevent the spread of Cu contamination to non-copper wafer-processing tools or shared manufacturing tools.
Acknowledgments
The authors would like to acknowledge the valuable contributions to this work from our colleagues in the copper development and manufacturing implementation team at Conexant Systems. We also would like to thank Dr. Diane Hymes and the applications team at Lam Research for their support in developing the post-CMP cleaning strategies and chemistries discussed in this article.
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Dieter Dornisch received his PhD in crystallography and his MS in chemistry from the Ludwig-Maximilians-University, Munich, Germany. He has more than 10 years of experience in thin film characterization, ultrapure chemical generation, post-CMP cleaning, CMP process development, and—more recently—in Cu electroplating process development and Cu defect reduction for advanced interconnects. Dornisch is senior staff engineer in the Advanced Process Technology Dept. at Conexant Systems Inc., 4311 Jamboree Road, Newport Beach, CA 92660; ph 949/483-5519, fax 949/483-6104, e-mail [email protected].
Guangming Li received her PhD in materials science and engineering at the University of Arizona, doing research on the electrochemical aspect of copper contamination during microelectronic processing. She joined Conexant after her graduation and has been working on CMP and cleaning process development, focusing on the various cleaning aspects of copper/low-k dual damascene process, including post-CMP clean, post-dielectric etch clean, and wafer backside clean for contamination control. Li is currently a staff engineer in the Advanced Process Development Dept. at Conexant Systems.
Maureen Brongo received her BS in chemistry from California State Polytechnic University of Pomona and her MBA from National University. She has 15 years of experience in process development, including photo, etch, planarization, and advanced interconnects. Brongo is director of module development and integration at Conexant Systems.
Effects of Cu contamination
Copper is extremely mobile in silicon and silicon dioxide [6, 7]. It exhibits the highest diffusivity in silicon among all metal elements. In ionized form in dielectrics it drifts readily under the influence of an electric field. When present in active device regions, Cu impurities could cause functional failures through a variety of mechanisms—increasing leakage currents or carrier recombination rates, forming localized precipitates that degrade gate oxide integrity and cause premature oxide breakdown, etc. [8]. In extremely sensitive devices such as flash memory cells and DRAMS, even small contamination levels can shorten retention times.
Although Cu has been used as a common alloy metal (typically between 0.5wt-% and 3wt-%) in aluminum interconnects to improve electromigration resistance and reliability, its use as a pure or primary interconnect metal generates a completely different set of requirements for containing Cu atoms. Cu atoms alloyed with aluminum are immobilized by the aluminum matrix, which acts as a very efficient getterer.