Ion Implantation: An improved secondary electron flood helps control ion implant charge
04/01/2000
Overview
The accumulation of surface charges on electrically insulating layers during ion implantation affects the yield of charge-sensitive devices. Experiments with a typical secondary electron flood system and refinements to it demonstrate that improvements can be made over some common secondary electron flood systems currently in use.
David A. Fleming, Celeste Mullis, National Semiconductor Corp., Arlington, Texas
High-current ion implantation equipment requires either a secondary electron flood (SEF) or plasma electron flood (PEF) system to neutralize the electrostatic potential of the beam of positive ions bombarding the wafer. If the beam is not neutralized, at least two significant problems will arise [1]. First, the beam will be difficult to control because of electrostatic repulsion within the beam itself. Second, electrically insulating materials on the wafer will become charged, resulting in such effects as oxide breakdown. The latter effect, especially, becomes more pronounced as gate oxide thickness decreases with successive generations of IC technology.
SEF has been the more popular approach for charge control because of the cost and process complexity of a plasma-based system. A SEF system consists of a source of high-energy electrons that impinge on a target, releasing secondary electrons in the appropriate energy range (about 10eV). These secondary electrons are captured in the ion beam and transported to the wafer surface, neutralizing the positive charging of the ion beam. It is critical that no high-energy electrons are trapped in the beam and transported to the wafer, because a high negative potential can damage thin gate oxides.
Previous-generation SEF designs allowed multiple mechanisms for the inclusion of high-energy electrons in the beam [1]:
- The negatively biased aperture that stabilizes transport of the positive ions can steer some primary electrons toward the wafer surface instead of their target.
- The source of primary electrons might not be tightly focused or might not have a very limiting aperture, allowing some primary electrons to impinge on an extension tube near the wafer, resulting in high-energy secondary electrons.
- The buildup of photoresist from the wafers on the extension tube might get negatively charged by the primary electrons and then accelerate the secondary electron to an undesirably high energy.
A SEF product that addresses these problems includes the following upgrades: moving the biased aperture away from the primary electron source and redesigning it to have a smaller negative bias; optimizing the aperture at the source of primary electrons; and redesigning the extension tube with a serrated surface to prevent the buildup of photoresist.
The present work contains experimental verification of the success of the improvements embodied in the Eaton 200E SEF.
Forward bias SEF
National Semiconductor previously used a Forward Bias SEF system to control charging in its ion implanters. This SEF uses an aluminum anode target and a vitreous graphite liner extension tube. The effectiveness of this charge control system was evaluated with in situ disk current monitors [2, 3]. More recently, CHARM2 wafers from Wafer Charging Monitors Inc. have been used to characterize implanter-charging effects that are undetected by disk current control [4-6]. CHARM2 wafers are test monitors used to characterize the charging voltage potentials and current densities associated with ion/plasma process equipment.
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Disk current response for Forward Bias SEF and 200E SEF, showing improvement in peak negative disk current. Each run includes 10 two-minute implants of 80keV As+ (12mA), varying primary current from 0-30x the beam current.
Charging during the implant process was minimized with rigorous preventive maintenance (PM) procedures and characterization, since the condition of components in the system can significantly affect its functioning. The main consideration is controlling resist buildup on the SEF components. It was found that any attempt to clean the vitreous graphite inserts resulted in buildup potentials increasing 500% as measured by disk current and charge voltage monitors. Therefore, the vitreous graphite extension tube and bias aperture should be replaced during PM.
Beam current optimization was the other key part of minimizing wafer charging. Process modifications were made to minimize the charging levels detected. The ratio of electron shower primary current to beam current (ES/BC) was changed from 10 to 5 for 40keV 7ma boron B11/BF2 processes, from 15 to 5 for 30keV 9mA arsenic processes, and from 15 to 5 for >30keV 12mA arsenic processes. The ratio was determined by the value that resulted in an acceptable charging range throughout the life of the shower between PMs. Acceptable charging ranges were defined by product tolerance and process windows.
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After the processes were updated with the optimized ES/BC ratio, there were still significant negative potentials detected by in situ monitors for charge voltages and disk currents. CHARM2 devices confirmed the negative potentials, which indicated that high-energy electrons were still getting to the wafers.
SEF modification
In the process of redesigning the Forward Bias SEF to reduce the negative charging potentials caused by high-energy secondary electrons, Eaton's first step was to have a serrated surface on the graphite extension tube. After a six-month beta test at National Semiconductor, the serrated tube was shown to reduce the negative charging by 5-10%. This improvement by itself was not enough to bring the negative potentials (measured by CHARM2 wafers to be around -30V) into an acceptable range.
At this point, options for further reduction of the high-energy secondary electrons were to install a PEF or to modify the existing SEF further. The PEF was ruled out to avoid increased complexity, the possibility of heavy metal contamination, potentially higher operating cost, and a significant learning curve associated with conversion to the PDF technology. Thus, Eaton continued its modifications of the SEF, including changes to the filament position and aperture, modification of the bias aperture, and a redesign of the graphite anode target to include a zener diode bias [1, 7].
Test conditions
An Eaton NV-GSD/200 high-current implanter was used to evaluate the redesigned SEF. The primary process used to evaluate the effectiveness of the new charge control system was a 12mA arsenic implant at 80-100keV with doses of 0.80-1.00 x 1016 ion/cm2. Although many charge-sensitive structures have been used to characterize charging potentials, the CHARM2 monitor was selected because it is available for use throughout the industry.
Measurements of crossover voltage—the condition at which the positive and negative swings of the beam potential are equal [6, 7]—were performed with the Forward Bias SEF and the 200E SEF for both arsenic (12mA at 80keV) and boron BF2 (7mA at 75keV). The 200E SEF crossover values were compared to clean Forward Bias SEF values to verify secondary electron efficiency. The crossover voltages were comparable and both were found to be at an ES/BC ratio of 10.
The test wafer sheet resistance performance was verified before and after the 200E SEF installation for 40keV boron B11, 75keV boron BF2, 30keV arsenic, and 80keV arsenic. All test wafer sheet resistance measurements were within 0.25W/sq (<0.5%) of one another with a 0.10% reduction in standard deviation after the 200E SEF installation.
Experimental results
Several articles have been written explaining how the CHARM2 monitor is used to measure the in situ charge distribution across wafer surfaces [4-6]. The wafers currently available to the industry typically measure voltage potentials in the range of 5-25V for positive potentials and -5V to -25V for negative potentials. A typical arsenic implant at the end of the Forward Bias SEF PM cycle using these CHARM2 wafers resulted in voltage measurements at -25V for more than 30% of the wafer, indicating complete saturation with respect to the negative potentials.
Before the CHARM2 monitor could be used to establish a baseline for the performance of the Forward Bias SEF, the detection range of the CHARM2 monitor needed to be expanded. The maximum voltage stored on the floating gate of an EEPROM on a CHARM2 monitor directly relates to the tunnel oxide thickness. Thus, increasing this thickness increases the storable voltage, augmenting the voltage amplitude over which the EEPROM reacts as a voltmeter. The disadvantage of increasing the tunnel oxide thickness is that the EEPROM does not react to low voltages, resulting in CHARM2 devices that now respond to the 8-38V range rather than the 5-25V range of the thinner oxide wafers. Because high-current implants typically result in negative potentials >-10V, CHARM2 monitors with thicker tunnel oxides were used to evaluate the Forward Bias SEF. The new CHARM2 monitors showed negative potentials as large as -34V. These CHARM2 monitors were then correlated to BiCMOS yield loss. The yield was found to degrade as the negative potentials exceeded -32V.
The table summarizes the charge control improvement gained by switching to the 200E SEF. The 200E SEF produced a 25% reduction in the peak negative potentials and a 39% reduction in the average negative potentials. The 3s distribution is reduced by 42% for the negative potentials. This reduction is a quantitative measurement of the improvement gained throughout the PM cycle using the 200E SEF. The largest negative potential is expected at the end of the SEF PM cycle; this value was -26V. No measurable positive charging has been observed using the 200E SEF with an ES/BC ratio equal to 5 for all processes.
The BiCMOS product manufactured at the wafer fab where these experiments were performed is susceptible to current leakage observed after high-voltage stress, a direct result of wafer charging caused during an arsenic source/drain implant. The BiCMOS gate oxide damage had been observed to occur at peak potentials smaller than -32V. After the installation of the 200E SEF, a limited volume of BiCMOS product was run between the two quarterly PM cycles, and the yield was nearly identical for the high-current NV-GSD implanter with the 200E SEF and the standard NV10 implanter. The fact that wafer-charging yield loss did not change with the higher-current implanter demonstrates that the charge control system was functioning effectively.
For real-time equipment-level control, disk current monitor readings and/or charge monitor readings should be used to predict the high charging potentials measured by CHARM2 in these experiments. Disk current linearity testing is a good tool to show how resist buildup affects the charging environment during the SEF PM cycle. The linearity test consists of 10, 2-min. implants performed over the shower operating window of 0-360mA. The series is run every 3 days during the PM cycle. Time plots of each implant set were created for disk current and charge monitor data.
The charge monitor loosely correlates with disk current readings. Charge monitor readings trend downward for positive voltages and upward for negative voltages. However, charge monitor sensitivity was insufficient to indicate high negative potentials shown by CHARM2. Disk current response proved to be a better indicator of SEF performance as measured by CHARM2. The figure on p. 63 shows a time plot of disk current data for each implant set for both the Forward Bias SEF and the new 200E SEF. The disk current data shows a 25% reduction between SEFs, which agrees with CHARM2 results shown in the table. Despite the correlation, CHARM2 verification is required because a disk current monitor cannot detect high-energy secondary electrons reliably.
Conclusion
A redesigned SEF system has been proven to be an effective option for decreasing the high-energy secondary electrons that reach the wafer surface. Using consistent PM procedures, the 200E SEF has been demonstrated to achieve a wide operating window for charge control. Real-time charge control can be achieved by use of the disk current monitor, with shower performance verification by scheduled CHARM2 monitors.
Acknowledgments
The authors thank Sang Troung and Conrad Bourg for their experimental contributions; Ron Reece and Rick Geraghty of Eaton Corp. for their support; John Griffith and Cleston Messick for their CHARM2 help; and Melanie Heasly for ensuring that the components for the SEF were available at the needed PM intervals. CHARM2 is a trademark of Wafer Charging Monitors Inc.
References
- Y. Erokhin, R.N. Reece, R.B. Simonton, "Charge control for high-current ion implant," Solid State Technology, Vol. 40, No. 6, pp. 101-110, June 1997.
- D.A. Fleming et al., "Real-time high-current implant charge control using disk current," Semiconductor International, June 1995.
- E. Kimber, US Patent Application, S.N. 08/133 746 NS2247 "Electron shower modification for disk current control."
- S. Reno et al., "A new technique for solving wafer-charging problems," Semiconductor International, July 1995.
- W. Lukaszek et al., "Characterization of wafer-charging mechanisms and oxide survival prediction methodology," IEEE International Reliability Physics Proceedings, 1994.
- R. Bammi, S. Reno, "Using CHARM2 wafers to increase reliability in ion implant processing," IEEE International Integrated Reliability Workshop Final Report, IEEE Cat. No. 95-TH-8086, 1995.
- R.N. Reece et al., "Optimization of the secondary electron flood design for the production of low-energy electrons," Proceedings of XII International Conference on Ion Implantation Technology, pp. 315-318, June 1996.
David A. Fleming received his BS in chemical engineering from Purdue University. He has worked in implant engineering for the past 12 years and is the manager of implant process engineering at National Semiconductor Corp., 1111 West Bardin Rd, Arlington, TX 76017; ph 817/468-6477, e-mail [email protected].
Celeste Mullis received her BS in chemistry from the University of Utah, and has engineering experience in diffusion, photolithography, electrical test, and ion implant. She is the manager of etch process engineering at National Semiconductor.
Why plasma electron flood?
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The secondary electron flood (SEF) has proven very effective for charge control of devices at the 0.35µm technology node, and this article is an excellent example of the recommended approach: optimization using actual device measurements. In many cases, for advanced devices with thinner gate oxides, the plasma electron flood (PEF) offers superior performance. Two main advantages that the PEF offers are lower electron temperature (<3eV) and direct coupling between the plasma and the ion beam via a plasma bridge. This leads to self-regulation of electron current, or "current on demand." This results in lower potentials on the wafer as detected by CHARM and less dependency of electron current on the environment, minimizing break-in effects.
Eaton's GSD/HEmc high-speed batch ion implanter.
Michael Ameen, Process Technology Manager, Eaton Corp.