Metrology: Requirements for dual-damascene Cu-linewidth resistivity measurements
04/01/2000
Overview
Understanding the complexities associated with copper linewidth electrical measurements, which are not as straightforward as those with aluminum, provides a viable means of metrology for dual damascene processing. The complexities of this method come from the required sidewall barrier. A sequence of resistance measurements on four different lines combined with a set of capacitance measurements, all done with adequately specified instrumentation, provides the solution.
Tim Turner, Keithley Instruments Inc., Solon, Ohio
Electrical measurements to determine metal linewidths have been well understood for many years. However, techniques used in the past assumed a constant sheet resistivity. This is not the case for copper (Cu) lines from dual damascene processing. These lines include a refractory barrier metal coating on sidewalls of the metal lines. The sidewalls have a sheet resistivity significantly different from the layer of Cu over the refractory metal that comprises the rest of the metal line, significantly complicating electrical measurement of linewidth.
With dual damascene Cu lines, the resistance of the line is the parallel combination of the resistance of the central copper-over-barrier line and the two sidewall barriers, which is calculated as:
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where RL is the resistance of the line, rCu is the sheet resistivity of the Cu layer on top of the barrier layer, WCu is the width of the line inside of the sidewall barrier layers, L is the length of the line between the voltage taps, and Rb is the resistance of the two sidewall barrier layers (i.e., Rb = 2rbL/Wb, where rb is the sheet resistivity of the barrier layer on the sidewalls and Wb is the width of the sidewall barrier metal or line thickness for the deposition of this film).
All three independent variables in the equation must be known to obtain the width of the metal line. Unfortunately, two of these variables are a puzzle. The resistance of the sidewall barrier films and a change in linewidth away from some target values will produce a resistance change in the line that is independent of linewidth (Fig. 1). It is impossible to determine how much of the resistance change is caused by each of these phenomena.
Further, the resistivity of the Cu layer can be significantly different depending on linewidth because the grain size of the line changes with linewidth (Fig. 2). Narrow lines tend to have much smaller grain size, resulting in a higher sheet resistivity [1]. Thus a simple measurement of the resistance of three different metal lines is not sufficient for the calculation of the three metal line parameters.
In addition, the width (thickness) of the sidewall barrier metal can decrease for very narrow metal lines (Fig. 3). If the total linewidth becomes less than about 4x the thickness of the barrier metal layer on a flat surface, then it is likely that the sidewall thickness will be less than the thickness of the metal film on the flat surface due to self-shadowing effects. Barrier metal layers are commonly ~500Å thick, so lines with a nominal width of about <0.2µm may show thinning of the sidewall barrier layer.
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Figure 1. Change in line resistance due to width variation is confounded by changes in barrier layer resistivity and thickness.
A final confounding effect comes from line thickness variation due to CMP processing. The assumption of a uniform line thickness is not valid in a dual damascene process. Variations in the amount of polish will change the line thickness at different locations on the wafer. In addition, dishing can make the line thickness a function of linewidth (Fig. 4). Compared to the oxide and barrier metals surrounding the Cu, wide lines tend to have greater thinning in the center of the line due to the faster rate of polish for Cu.
Van der Pauw sheet resistivity
A simple Van der Pauw structure (i.e., a box cross) can be used to measure the Cu-barrier metal sheet resistivity directly (Fig. 5). A Van der Pauw structure is essentially the intersection of two metal lines enlarged with a square around the intersection point. Current (I) is forced between two adjacent lines and the voltage drop (V) is measured between the other two lines. The sheet resistivity will then be calculated as [2]: rCu = 4.53 (V/I).
For large boxes, this measurement is only the sheet resistivity of the Cu over the barrier layer; sidewall metal layers have no impact on this measurement. The voltage drop is measured directly across the Cu without going through the barrier material, and the current path cuts across the center of the box, making the contribution of the sidewall barriers insignificant. This resistivity applies to only wide lines (3x average grain size), and may not be representative of the Cu-barrier resistivity in narrow lines. Thus, the measurement represents the Cu-barrier sheet resistivity only for large boxes (box side >100x total sidewall barrier width). As the box becomes smaller, the sidewall impact increases, creating a source of error for the Cu-barrier sheet resistivity measurement.
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Figure 2. Wide lines tend to have larger grain size, and larger grain size lowers sheet resistivity.
Using two different sizes of box cross structures (e.g., 100x and 200x total sidewall barrier width) allows measurement of the effects of CMP dishing. Larger crosses will show greater dishing effects and therefore higher sheet resistivity.
Measurement requirements
Box-cross-structure measurement may be limited by instrument voltage resolution. The instrument must be able to measure voltage drop accurately across one square of resistance divided by 4.53. Assuming a Cu sheet resistivity of 0.02Omega/, the voltmeter must be able to resolve a voltage drop across 0.0044Omega.
The current that can be forced through the line is limited to less than the current density that causes joule heating in the metal line connecting the probe pad to the box cross structure. (It is not limited by joule heating caused by current density in the box, but only by current density in the narrower connecting lines.) Heat generated in the connecting lines will be easily conducted to the box area. The small thermal mass of this structure and the good thermal conductivity of Cu ensures that the Cu box will rise in temperature as connecting-line temperatures increase.
The thermal coefficient of resistance for Cu is ~0.36%/°C. Therefore, each degree of temperature change will cause a 0.36% change in the resistance of the box. Heating by as little as 14°C will create a 5% error in the sheet resistivity measurement. Further, lines with CMP dishing and smaller linewidths will have higher resistance. These lines will show a greater amount of heating and a greater error in the resistivity measurement.
Consider a 3.0µm metal line that connects the probe pad to the box cross structure. This line has a sheet resistivity of 0.020Omega/ and sits on a 1µm layer of SiO2 on silicon. The thermal resistance of this structure will be ~0.022°C/W/cm2. If the line in the conductive path is 150µm long, then the resistance of the line will be 1Omega. The area of the line will be 450µm2. The maximum current in the line is defined by [3]:
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where Imax is the current that raises line temperature by 1°C, w is linewidth, r is sheet resistivity, and Rthermal is thermal resistance.
For the example above, the maximum current will be 14.3mA, at which the voltage drop across 0.0044Omega (the box resistance) will be about 63µV. If the measurement is expected to determine sheet resistivity with a 5% resolution, then the voltmeter must have a resolution and noise level better than 3.2µV. If the width of the connecting line is doubled to 6µm, then the forced current, and the required voltage resolution and noise levels can all be doubled. Each side of the box should be at least 5x the width of the connecting line, so the box dimensions would be at least 30µm/side. In addition, the length of the connection line extending out from each side of the box should be at least twice the width of the connecting line before a turn or connection is made [2].
Increasing box dimensions to the point where each side and its connecting line is limited only by a typical 80µm-wide scribe lane, the maximum box dimension is ~36µm and the maximum connecting linewidth ~7.2µm. This provides the best case structure as far as required voltage resolution and noise is concerned (i.e., ~7.5µV). Table 1 compares structure dimensions and measurement parameters.
Measurement noise at these levels can be achieved only through very careful instrument design, plus averaging multiple readings or the integration of an acquired signal over several power line cycles (PLCs). For example, a Keithley Model S630 automated parametric test (APT) system uses pin electronics in the probe card adapter to achieve a voltage resolution of 100nV and a noise level of <10µV with a signal integration period of one PLC. To make the best case measurement mentioned above (noise level <7.5µV), the instrument's source-measurement units (SMUs) must be programmed for a two PLC integration period. (The longer the integration period, the lower the instrument throughput.)
Structures and measurements for confounded variables
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Figure 3. Very narrow lines typically show thinning of sidewall barrier metal layers.
The impact of sidewall barrier thinning on very narrow metal lines and the impact of Cu resistivity changes from grain size reduction in narrow metal lines are still confounded. However, we can make an approximation of the impact of these two parameters as long as the average Cu grain size for wide lines is greater than about six times the barrier thickness over a flat surface.
This approximation can be made by modeling the Cu line as two parallel resistors:
- R1 is the Cu line on top of a sheet of barrier metal.
- R2 is the sidewall barrier metal resistance and the difference in resistance between a metal line with the designed linewidth compared to the actual metal linewidth.
As noted above, the resistance variation caused by the difference between designed and actual linewidth and the resistance variation caused by changes in line thickness and resistivity of the barrier metal are inextricably confounded. For the evaluation of the sidewall thinning and Cu grain-size effect, however, a single combined parameter can be determined using:
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We can determine the effect of the Cu grain size using two metal lines. The first line should have a linewidth >5x the nominal Cu grain size, the second a width <2x the nominal Cu grain size (so it will show grain shrinkage), but >6x the barrier metal thickness over a flat surface (no sidewall thinning). With these limitations, 1/R = (W - 2t)
Cu L + 1/R2 provides a reasonable approximation of grain size effect.
The resistance of the wide line provides a measure of 1/R2 with the Cu resistivity (rCu) assumed to be that measured with the box cross structure. The measure of the second line then provides a measure of the resistivity of the Cu for small grain sizes using the 1/R2 value calculated from the first measurement. It is not necessary to know the exact linewidth to make this measurement. The percentage difference between Cu resistivity measured with the box cross method and measured using the narrow line can be used to calculate a "percent degradation" from grain shrinkage.
We can determine the effect of sidewall barrier thinning by comparing the resistance of two additional lines. One of these should have a linewidth >6x the thickness of the barrier layer over a flat surface, but less than the narrowest of the first two lines described above. The other additional line should have a width <4x the barrier metal thickness. The reduction in Cu resistivity with linewidth can be modeled by first calculating rCu for the wider of these two additional lines by using 1/R2 = [(DeltaW)
Cu + (h c)
B]/L. Using the linewidth and resistivity calculated from the narrowest of the initial two lines, and the linewidth and resistivity calculated for the wider of the second two lines, a resistivity slope with linewidth can be calculated (DeltarCu/Delta linewidth). Once this slope is calculated, the sheet resistivity of the narrowest test line can be predicted. Once the rCu is known for this line, 1/R2 can be calculated. Once 1/R2 is known, the equation just cited can be rewritten to calculate barrier thickness:
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DeltaW is measured using the capacitance measurement technique below and rB is known from in-line measurements.
Parametric tester resolution, accuracy
Consider a set of four metal lines for a process where the nominal Cu grain size is ~0.7µm, the thickness of the barrier metal over a flat surface is 0.05µm, and the minimum metal line width is 0.18µm. All the lines are 100µm long and sit on a 1.0µm-thick layer of SiO2 on silicon — a metal thermal resistance of 0.022°C/W/cm2. To evaluate change in Cu resistivity with grain size, we design one metal line with a width at least 3.5µm (5x nominal grain size). Another line is designed with a linewidth <1.4µm (2x grain size), but >0.3µm (6x barrier metal thickness). Here, conservative choices are 4.0µm and 0.7µm.
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Figure 4. CMP dishing can reduce thickness of wide metal lines.
The other two lines for evaluation of barrier metal thinning must be designed with >0.3µm (6x barrier metal thickness) and <0.2µm (4x barrier metal thickness). Conservative choices are 0.35µm and 0.18µm.
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Figure 5. Box cross structure for sheet resistivity measurement, where sidewall barriers have little impact on measurement.
As discussed above, the maximum current that can be forced through a metal line is limited, to prevent joule heating. From our Imax equation, the maximum current that can be forced through the 4.0µm line is 19mA. Similarly, the maximum calculated currents for other linewidths are 1.0µm: 4.8mA, 0.35µm: 1.7mA, and 0.18µm: 859µA. These current limitations are based on an assumption of a constant sheet resistivity of 0.02Omega/. However, this is not a valid assumption for narrow metal lines, where up to half the linewidth can be composed of barrier metal with a higher resistivity. Therefore, the current limitations for narrow metal lines must be reduced to about 0.85mA for the 0.35µm-wide line and 0.43 mA for 0.18µm.
The expected resistance of the 4.0µm-wide line is ~0.51Omega. The expected resistances for the 1.0, 0.35, and 0.18µm lines are about 2.2, 8.0, and 19Omega, respectively. At the calculated test currents, the voltage drop across the four lines, from widest to narrowest, will be about 9.7, 10.6, 13.6, and 16.3mV. These should be easy measurements for most parametric testers. Different measurements between pairs of lines are more challenging, however. Generally, this difference will be in the neighborhood of a few millivolts. Since it is desirable to have 1% resolution on the difference, the measurement uncertainty should be in the range of 0.1%. This requires measurement noise and resolution levels <10µV and current source accuracy of 0.1%.
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Automated parametric test (APT) systems should include instrumentation and test head designs that provide this level of resolution and accuracy, or better.
Linewidth measurement
The confounding of sidewall barrier resistance with a variation in resistance caused by linewidth prevents a simple calculation of the width based on a set of resistance measurements. The alternative is to use a set of capacitance measurements. On the other hand, measurement of metal capacitance includes parasitic effects that can be difficult to predict or measure. Fortunately, most of these can be normalized by taking a differential measurement of two very similar capacitors.
The two capacitors should be constructed of fingers of the layer in question, each structure having the same number of fingers with identical spacing. The only difference should be in the width of each finger. Using the same number of fingers and the same space between fingers normalizes the fringe effects from the sidewalls of the capacitors. If possible, the layer in question should be enclosed between plates of conductive layers both above and below the layer to be measured. Both the top and bottom plates should be connected together to reduce variation caused by changes in the layers below the metal.
With the differential structure described (Fig. 6), we can write equations for metal linewidth:
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where C1 and C2 are the measured capacitance of structures 1 and 2, W1 and W2 are the designed linewidths of structures 1 and 2, and DeltaW is the difference between the designed linewidth and the actual linewidth. The only potential interaction from this technique is the possibility that the dielectric thickness will be different, depending on linewidth. Minimizing the difference between the two linewidths can reduce this potential issue. Generally, the difference should be small compared to the space between the lines (1/10). This reduction in linewidth difference introduces a tighter requirement of the signal-to-noise ratio of the capacitance measurement.
Consider a pair of metal-one test structures designed to fit into a scribe line with drawn finger linewidths of 0.2µm and 0.3µm. The linewidth needs to be measured within ±0.01µm (5%). The fingers are spaced 1.0µm apart and there are 100 fingers, each 80µm long with a connecting line 1.0µm, adding another 110µm2 to the structure.
The test structure is built between a polysilicon plate separated from the fingered structures by a 1.0µm-thick dielectric (k = 4.0). The top of the fingered structure is covered with a large plate of metal-two separated from the finger structure with a 1.0µm-thick dielectric (k = 3.6). The metal-two and polysilicon layers are connected together around the perimeter of the structure with a few vias, so the impact of these connections on the measured capacitance can be ignored.
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Figure 6. Capacitance measurements made in scribe lines to determine metal linewidth. Different widths require the same number of fingers and the same spacing between fingers.
The surface area of the metal-one structures are 1710µm2 and 2510µm2 as drawn. With these areas, the nominal difference in capacitance between the two structures would be based on an area difference of only 800µm2, which translates to about 54fF. The measurement of this difference will determine the accuracy of the change in linewidth measurement. Therefore, the noise and resolution for this measurement must be <5% of this value (±2.7fF). For most instrumentation, a noise level this low will require the averaging of multiple readings. With averaging, the noise will be reduced as a function of the square root of the number of measurements; for example, averaging four measurements will reduce the noise by a factor of two.
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There should be little frequency or voltage dependence in this measurement. Making the measurement at 100KHz with 45mV RMS should provide a good measurement of this capacitor structure.
Conclusion
The measurement of linewidth and resistivity of Cu lines produced with dual damascene processing is much more complicated than previous technology using aluminum metal lines. The required sidewall barrier layer complicates the process significantly. However, a sequence of resistance measurements on four different metal lines, combined with a set of capacitance measurements, can be effectively used to measure metal linewidth and resistivity over a reasonable range of linewidths. This technique also allows the measurement of Cu resistivity change with linewidth, CMP dishing effects, and reduction in sidewall barrier thickness for very narrow metal lines. Instrumentation requirements for making these measurements are summarized in Table 2.
References
- X. Lin, D. Pramanik, "Future interconnect technologies and Cu metallization," Solid State Technology, Oct. 1998, pp. 63-79.
- M. Buehler, "Introduction to Test Structures," Tutorial Short Course, 1996 ICMTS.
- T. Turner, "Electrical Measurement of IC Device CDs and Alignment," Solid State Technology, June 1998, pp. 115-118.
Timothy Turner received a BSECE from Clarkson College of Technology. He has lectured on wafer level reliability for the University of Southern California Extension Center and on semiconductor process control for yield and reliability improvement at UC Berkeley and Chou Tung University in Taiwan. He previously owned and operated Turner Engineering. Turner is director of structures engineering at Keithley, Semiconductor Division, 28775 Aurora Rd., Solon, OH 44139; ph 440/248-0440, fax 440/498-2895, e-mail [email protected].
COPPER PROCESSING
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Turner's work fills a need in copper process development
Keithley's model S630 automatic parametric test system
Grain size in copper (Cu) dual-damascene processing is not easy to control. This affects the linewidth and resistivity of Cu lines at back-end processes, such as etching and CMP. We've needed a good test method and adequate test instruments to pinpoint weak processes. The right test data needs to reflect the process impact and provide an indication of uniformity problems on a wafer. Tim Turner's work in providing good test metrology to solve the Cu-resistance effect has added to copper-process technology development, specifically helping researchers tweak process quality as it is manifested in resistance, leakage, and sidewall parasitic capacitance, all parameters that tremendously impact IC performance. He has uncovered for us some great pattern-design ideas that promote detection ability at back-end Cu processes. This technique can also be applied to accurate measurement with two composed metal layers.
Dr. Mu Chun Wang, characterization and parametric test manager for R&D, UMC, Hsin-Chu, Taiwan