Technology News
04/01/2000
Roadmap-caliber BiCMOS from TI
Texas Instruments (TI) has adopted a bipolar CMOS (BiCMOS) process that uses >>silicon-germanium (SiGe). This semiconductor fabrication technology targets radio frequency (RF) applications for wireless telephony, providing roadmap-caliber RF transistor solutions (see table) for optimal integration, partitioning, and power consumption for future high-performance systems.
 |
Briefly described, the initial TI SiGe BiCMOS process technology features RF bipolar devices with 0.25µm drawn transistor gate lengths and 3V CMOS with 0.35µm drawn transistor gate-lengths. Products from this process are in development with volume shipments scheduled for 3Q00. Beyond this, plans are in place at TI to move the initial process to advanced CMOS nodes referenced on the 1999 International Technology Roadmap for Semiconductors (ITRS). Bill Krenik, TI's worldwide RF products manager, says, "Since this TI process efficiently integrates the bipolar device into the basic CMOS flow, it is among the most cost-efficient SiGe technologies yet announced."
From a systems point of view, TI's new SiGe process technology allows designers to implement advanced wireless designs. For example, with chips fabricated on the TI SiGe BiCMOS process, <20µA can achieve an fT (unity power gain frequency) of 25GHz — one-third less power consumption than that of other processes announced to date. Peak fT is quoted at >50GHz. Noise is also notably low: <0.5dB at 2GHz. The SiGe BiCMOS process also enables greater-density integration of passive components, an important factor in component counts for advanced wireless architectures. The 1999 ITRS identifies integration of precision passive elements as "increasingly difficult with increasing values of inductance and capacitance, and operations at lower voltages."
Krenik says, "Advanced wireless standards use complex modulation techniques to enhance network capacity for both voice and high-speed data and operate at RF frequencies up to 2.5GHz. These next-generation standards demand higher RF signal fidelity with less power consumption. SiGe-based components operating at these high frequencies provide superior noise and linearity performance at significantly lower power consumption than do pure silicon-based components."
While TI will not elaborate on manufacturing details, the new process has "added minimal process complexity to the company's advanced CMOS processes with just five additional masking steps beyond the basic CMOS flow to achieve 50GHz fT."
Plasma doping progress
Low-energy plasma doping is pushing the envelope on shallow junctions, with reports of implants and junction depths below the limits of detection for standard SIMS equipment. Susan B. Felch of Varian Semiconductor Equipment Associates gave an update on progress with plasma doping at the Greater Silicon Valley Ion Implant User Group session at the American Vacuum Society's 2nd International Conference on Advanced Materials and Processes for Microelectronics.
Typical plasma doping (PLAD) processes use a voltage in the range of 1000-5000V to pulse the wafer and draw the dopants out of the plasma above the wafer. Low-energy PLAD uses voltages on the order of 100V to draw the dopants out of the plasma with much less acceleration, resulting in much more shallow implants. With 140V, Felch achieved an as-implanted depth of 70Å at 1 x1018/cm3 Boron concentration. The most recent result reported was a successful 80V implant, which resulted in a 50ohm/square sheet resistance. The junction depth has not been measured yet because it is beyond the limit of SIMS to detect. This work provides encouraging evidence that some of the goals on the ITRS Roadmap are achievable.
IC manufacturers have evaluated devices made with plasma doping, and they have seen positive results. AMD saw device characteristics improve by 5-10% compared to those made with ion beam implants, and Samsung saw similar results with 0.18µm devices. Felch attributes the improved performance to a longer, flatter plateau in the depth profile seen after annealing, compared to a beamline implant. This trait of the PLAD comes from the range of energies of the ions implanted in the material. With a beamline implant, the ions are mono-energetic, so they will cluster closer together with larger concentration gradients. The spread of energies created by PLAD leads to a larger region with the desired concentration. This profile-dependent performance demonstrated the need for improved metrology.
In the same session at the AVS conference, Michael Current of Silicon Genesis also pointed out the need for tools that measure the profile of electrically activated dopants in a nondestructive, in-line manner. Measuring just the dose is no longer sufficient when different doping processes result in significantly different types of profiles.
Felch also reported on applications of nitrogen PLAD. Gate dielectrics and stacked capacitors could be fabricated with this technology. Nitrogen can also be used as a "pre-implant" to reduce the diffusion of other dopants.
Finally, in a discussion of future trends, Silicon Genesis' Current presented plasma doping as a key technology for moving beyond the Roadmap. PLAD or plasma immersion ion implantation (PIII), as Silicon Genesis calls it, will be required for the conformal doping that will be needed to fabricate the vertical structures at the end of the current roadmap. The directionality of an ion beam with standard ion implantation will not work for the sides of vertical structures. Thus, plasma doping could be one technology that moves us along the Roadmap and stays with us beyond it.
50nm gates via optical lithography, OPC advances
In time for an announcement by Michael Fritze of MIT Lincoln Laboratory at the 2000 SPIE International Symposium on Microlithography, record-breaking 50nm transistor gates have been achieved using Numerical Technologies Inc. (NumeriTech, San Jose, CA) phase-shifting technology and 248nm DUV optical lithography. The devices were fabricated at MIT Lincoln Laboratory (Lexington, MA) as part of a DARPA-sponsored program on sub100nm fully depleted SOI CMOS.
Once again, this result demonstrates the potential for existing optical lithography tools to generate feature sizes significantly smaller than originally anticipated. Y.C. "Buno" Pati, president and CEO of NumeriTech, says, "People have been predicting the end of optical lithography for several years, saying that it can't extend beyond 100nm. But this work proves that with prudent use of phase shifting, optical lithography can be extended much further than anyone ever thought was possible."
In other news, NumeriTech has introduced a new optical proximity correction (OPC) technology dubbed iN-Tandem, a new physical design tool that improves the manufacturability of subwavelength IC designs. Unlike other methods of OPC that use either a rule-based or model-based approach, iN-Tandem uses a combination of both approaches to achieve high-quality results in a short amount of time. The product also includes a silicon vs. layout verification capability to verify the layout of a subwavelength IC against the silicon it is intended to produce.
Rule-based OPC operates from a detailed set of design rules and provides a fast corrective approach with minimal expansion of data volume. However, applying rule-based OPC on a whole chip, although sufficiently accurate for most of the chip, may not have the necessary accuracy for certain performance or yield-sensitive areas of the chip because rules typically do not cover every instance in a design.
Model-based OPC uses process simulation to apply OPC where needed. It is ideal for dense design structures such as memory cells or datapath. It is extremely accurate, but can take a long time to run over the entire chip. It also adds to the data volume, making mask creation and repair expensive and time-consuming.
Straight application of either rule-based or model-based OPC across the chip leads to the application of too much OPC due to its "global application" approach and leads to unnecessarily complex masks that are expensive to create and require a long time to produce.
iN-Tandem's hybrid approach uses a selection engine that divides the design into those areas that are best suited for a rule-based approach and those that are best suited for a model-based approach. It makes the determination based upon built-in intelligence (i.e., heuristics) that considers location, geometry style, and density of the regions of the IC, or by user-defined scripting. Then the rule-based and model-based OPC engines are run "in tandem" to apply the optimal amount of OPC to the various areas. iN-Tandem can also run in an all rule- or all-model-based mode if the design is suited to a single approach.
The corrected design is then verified using iN-Tandem's silicon vs. layout verification engine for a final check. The layout is simulated against the various process effects, such as optical, chemical, and etch effects. The simulated silicon image is then compared with the intended layout. If further correction is needed, it can be completed through the iN-Tandem model-based OPC engine.
Sub-100nm features with conformable contact photolithography
Re-designing a lithography method from the past, researchers at Massachusetts Institute of Technology (MIT) have recently demonstrated that 100nm features and below can be patterned readily with conformable contact photolithography (CCP, see Fig. 1); this work has been supported by the Space and Naval Warfare Systems Center (San Diego).
The technique is said to be low-cost, and it avoids shortcomings of other contact-lithography methods, which include the ability to pattern truly arbitrary shapes; to pattern large and small features simultaneously; the propensity for pinhole defects; lack of mask durability; ability for precise mask-to-substrate alignment; and printing-induced pattern-placement errors. James Good-berlet at MIT states,
"We have patterned uniform isolated linewidths down to 100nm with ±18% dose latitude for ±9% linewidth control at 116nm."
The need for advanced contact lithography is found in some applications of ASICs, integrated-biotech devices, microelectromechanical systems, academic research, and very-high-density data storage. Goodberlet says, "In some of these applications, small companies or research labs require a method to make quickly a limited number of samples for little expense."
Briefly described, CCP uses a 220nm-wavelength HgXe arc-lamp source. The mask — dubbed embedded-amplitude mask (EAM, Fig. 2) — consists of a 40nm-thick patterned chrome absorber embedded into a 150µm-thick conformable UV-transparent silica substrate; it is fabricated with electron-beam lithography and a tri-layer resist stack. Goodberlet explains, "The thinness of the mask's substrate and a vacuum fixture assures that the mask intimately contacts the substrate, which is essential for good pattern replication. Further, the embedding of the absorber enhances the optical-printing resolution by taking advantage of the substrate's high refractive index — effectively shortening the optical wavelength."
 |
Figure 1. Chrome-on-silicon patterns fabricated with CCP: a) 77nm-wide nested Ls, 200nm pitch, gb) pad-and-gate with 140nm gate length, c) coarse-and-fine features patterned simultaneously, and d) a 200nm-pitch grating.
Overall, the optical field propagates non-evanescently between openings in the patterned absorber as narrow as l/2n, where l is the exposure wavelength and n is the refractive index of the mask's substrate. "We have determined the practical resolution limit for CCP with the EAM as k l/2 where the value of k depends upon materials used for the EAM and resist properties, but is in the range of 0.6 to 0.8," says Goodberlet.
Sub-20nm, multilevel alignment presents a formidable challenge for CCP, but appears to be an obtainable goal using the EAM and advanced alignment techniques. The optically transparent mask is suitable for through-the-mask alignment. Importantly, the EAM has high
in-plane stiffness that greatly reduces pattern-placement errors. On successive prints with the EAM, the printing-induced pattern-placement errors have been measured to be <60nm, which was the detection limit of the measurement apparatus. Goodberlet says, "The actual errors are expected to be significantly smaller. Small placement errors are essential for applications requiring multilevel alignment at 100nm feature sizes."
 |
Figure 2. The EAM consists of a DUV-transparent, 150µm-thick substrate bonded to a semi-rigid plastic annulus for improved durability and handling. Here, the thickness of the mask's substrate has been exaggerated to depict the embedded absorber.
Recent modeling suggests that arbitrarily shaped features down to 70nm can be patterned readily with a 220nm-wavelength source. "Interestingly, the slope of the linearity is less than unity, which indicates that mask errors would be reduced during the printing process. Comparison of mask and replicated patterns verify that small linewidth variations on the mask are reduced on the wafer. This corresponds to a mask error enhancement factor of 0.6, and relaxes constraints on mask fabrication," explains Goodberlet.
Problems with particles and throughput do not appear to be major hurdles for CCP. Particles can be detected before exposures and can be removed from the mask if necessary. Further, since the mask is conformable, the defect area caused by particles extends over a limited range. Through-put for CCP is limited by the mask size for a single-exposure tool or the ability to contact and release quickly the mask and substrate for a step-and-repeat tool. With a sensitive DUV resist, the exposure rate can be as high as 40cm2/sec with a 500W HgXe lamp.
Currently, the largest available mask size is 50mm diameter. With this mask, an aligned step-and-repeat printing rate of about 10 cm2/min is estimated. Although well below values of throughput for conventional steppers, this rate may be acceptable for many limited-lot applications. The cost of a CCP exposure tool is expected to be less than $50K. Goodberlet states, "At least, CCP can make sub-100nm fabrication available to many entities that cannot afford a multimillion dollar optical-projection-lithography stepper. Right now, we believe this method will find numerous applications in research and small-business ventures."