System-on-a-chip: What industry needs to do
03/01/2000
Cor A. Scholten
The integration of system functions and even entire systems onto a single chip is now feasible. While there are advantages, there are also drawbacks to the system-on-a-chip (SOC) approach, and further development is needed in areas such as design methods, packaging, and testing. Industry needs to accelerate these efforts because of the great potential SOCs offer for important new applications.
Until recently, semiconductor demand was dominated by the personal computer (PC) market. But a shift is now taking place toward consumer electronics, communications infrastructure, and a host of portable business/personal devices. Together these emerging markets are overshadowing the one-time dominance of the PC industry as a driver for semiconductor technology, and their needs are often quite different than those for personal computer designs. But existing barriers are slowing the move toward SOCs.
Consider the potential: Using SOCs allows smaller, lighter devices with less power consumption — all desirable for portable and pocket-sized products. Prices can be lower as well, even with added functionality, especially if standards develop so that similar circuit functions can be designed into many types of devices.
These advantages are already being tapped. Single-board computers (SBCs) can be replaced by devices like Cell Computing's CardPC, using double-sided printed circuit boards and only 2 connectors instead of 20, in about one-sixteenth the space. But this miniaturized device costs about $400, compared to $150 for a computer motherboard. Now, if the functions are packed onto a single chip, as STMicroelectronics did with its STPC, using ball-grid-array (BGA) packaging with 388 I/Os and a few additional outboard passive and active components, the size is once again shrunk to about 7% of that of the CardPC, and the price is only about $40. Although these integrated systems have less functionality than a full PC, they are more than adequate for a wide range of applications.
There are additional advantages to the SOC approach. Fewer components can mean improved reliability, simpler logistics, and lower assembly costs. There is less I/O between the SOC and the substrate, and by putting the data bus structures onto the chip, the PCB can be smaller and simpler. RF properties are better as well, which is particularly important for wireless devices.
What are the barriers preventing many more systems designers from going the SOC route? More complexity means longer development times, and huge investments are required, including extensive engineering efforts with high-level skills, such as the use of sophisticated automated design tools. Since more process steps are involved, there can be yield problems, and there is less flexibility in design. If both analog (bipolar) and digital (CMOS) circuits are needed on the same IC, different process technologies are required, and it is difficult to handle high- power applications. Advanced packaging technologies are also involved, including exotic materials, bumping/joining techniques, and deposition and etching processes.
Extensive work is going into reducing or eliminating these barriers so that the potential for SOCs can be realized. Speeding design cycles is one major goal. Multidiscipline efforts are being applied to improving automated design tools, including adding knowledge about materials interactions as devices shrink. Flexibility is being improved in both IC design and fabrication, including work on hardware/software interfaces, to enable more diversity in application.
Materials with good heat transfer properties are being found for power devices, and processing technology is being advanced so that different power applications can be designed onto a single chip. Work on package designs should enable use of proven PCB assembly methods, such as reflow soldering. Miniaturized module assemblies using wafer-scale components are being developed for attachment during final PCB assembly. A new generation of surface-mount device placers will be required to assemble these modules, offering high placement accuracy (5-10µm) and low contamination. These modules will be suited for new placement methods, possibly using ceramic or flexible substrates. Although there are a wide range of packaging requirements for different applications, the industry needs to develop some standard packages that will encourage assembly equipment vendors to build the automated systems required.
The potential for SOCs to broaden product offerings, with higher functionality at lower cost, in smaller packages with lower power drain, makes it worthwhile for the industry to tackle the remaining challenges. Further development could achieve rapid design cycles, some flexibility in design, and standardized packages and assembly methods to gain economies of scale. It will be worth it.
Using SOCs allows smaller, lighter devices with less power consumption — all desirable for portable and pocket-sized products.
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Cor A. Scholten is managing director of Philips Electronic Manufacturing Technology, Luchthavenweg 75/Bldg. HVM, 5600 MD Eindhoven, The Netherlands; ph 31/40-272-4733, fax 31/40-272-3447, e-mail [email protected].