CMP: Spin-etch planarization for dual damascene interconnect structures
03/01/2000
Donald S. DeBear, SEZ America Inc., Phoenix, Arizona
Joseph A. Levert, Shyama P. Mukherjee, Honeywell Electronic Materials, Sunnyvale, California
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Dielectric erosion is an existing issue for copper damascene chemical mechanical planarization even when hard dielectric materials such as dense SiO2 are used. A noncontact, non-slurry planarization process would provide distinct advantages for existing technologies as well as for future-generation, porous, ultra-low-k dielectrics that will be more susceptible to mechanical damage during chemical mechanical planarization. One such process in development is "spin-etch planarization," a wet-etch process using no physical contact with the wafer surface. Progress on this work is presented here.
The SEZ Spin processor 203 with edge-contact-only Bernoulli handling system performs silicon etch on 200mm wafers for advanced packaging applications. Photo courtesy of The SEZ Group
Dual damascene copper electroplating has been recognized as the metallization process for future IC interconnection technologies [1]. Current post-deposition planarization is accomplished using chemical mechanical planarization (CMP) for both the copper and the barrier metal(s), typically tantalum and tantalum nitride [2]. The desired process results include:
- complete removal of copper and barrier metal(s) from the field area dielectric surfaces;
- accurate planarization of the inlaid damascene features with the top surface of the dielectric; and
- no damage to field area dielectric surfaces.
Subsequent CMP of the surface of the underlying dielectric is often necessary in order to minimize unwanted side effects of the mechanical component of this technique, such as the nonplanar result known as "dishing." CMP for dual damascene plated structures has several disadvantages and intrinsic limitations, because it is inherently prone to cause dishing, erosion, and particle contamination. Another limitation of CMP results from mechanical rubbing of ceramic slurry particles on the final exposed surface materials of the damascene layer. This rubbing process can cause scratching of dielectrics and smearing of material from soft, copper-filled areas.
Noncontact planarization
Current R&D activities are focused on the development of a noncontact planarization method that can overcome the limitations and disadvantages of CMP processing. This development is also designed to allow the integration of ultra-low-k materials into the dielectric stack for future-generation process flows. The current work presents a novel planarization approach, spin-etch planarization (SEP), based on the controlled removal of metal layer(s) by exposure to a reactive chemical solution while the substrate is spinning. The etching of metal occurs in a controlled manner, leading to a low variation of the removal rate across the wafer, and to local planarization of the surface topography of the electroplated copper.
Click here to enlarge image Figure 1. Both of these copper-plating situations can be planarized with SEP.
During SEP, the wafer is suspended horizontally on a nitrogen cushion above a rotating chuck. The substrate is held in place laterally with locking pins on the wafer edge. As the chuck and wafer are spun, wet-etch chemistries are dispensed onto the wafer. An appropriate etching solution and the spinning of the wafer result in a planar final surface. The chemical etchants have no particulates, so the copper surface being planarized has no mechanical contact with any solid surfaces or slurry particles. This technique is inherently applicable to polymeric or other surfaces that have a low modulus or low abrasion resistance. Deionized water and nitrogen are then applied to the wafer to achieve rapid cleaning and drying, eliminating the need for post-process scrubbing and "wet" handling of wafers. The system is designed with multiple chambers to provide the multistep capability necessary for barrier materials.Recent work [3, 4] presented the details of the spin-etch tool and some processing information. Preliminary results on the uniformity of copper removal and the planarization of fine features on patterned wafers having nearly conformal plating have been documented [3].
Click here to enlarge image Figure 2. Etch rate and within-wafer nonuniformity (WIWNU) after SEP removal of copper from ECP and PVD blanket wafers, by run number.
The present work summarizes results with spin-etching of blanket copper wafers, including data on the planarization of different types of copper-electroplated, patterned materials. One set of wafers was created with a conformal electroplating technique (see Fig. 1 above). The second set of wafers was created using a superior trench-filling scheme designed to provide an improved surface profile or topography, especially in areas with larger pattern openings (Fig. 1). This plating technique left raised protrusions over small-feature trenches. With this process, called "superfilling," the electrodeposition takes place at higher rates in the bottom of features as compared to the sides. The current results indicate that planarization of either type of electroplating technique can be accomplished by spin-etch processing.Baseline process parameters and chemistry
Preliminary experimentation on etchant chemistries was conducted in order to determine a solution that would provide reasonable etch rates (for process throughput) while also delivering a highly polished surface finish (surface roughness equal to or less than that of the as-deposited surface). Further tests were performed to derive the process recipe necessary to minimize the nonuniformity of the etch rate across the wafer surface. These tests were performed on blanket electrochemical-plated (ECP) copper and physical-vapor-deposited (PVD) copper films on 200mm prime substrates with underlying oxide and barrier metal. Evaluations of selectivity to typical barrier metal and dielectric materials were conducted using 200mm blanket PVD tantalum, PVD tantalum nitride on thermal oxide, and 200mm thermal oxide wafers. Subsequently, testing with patterned electroplated copper wafers was performed to determine the degree of planarization while using the chemistry and process parameters developed during blanket wafer experiments.
Process metrology
Process results are reported as averages and standard deviations. Within-wafer etch nonuniformity was calculated using three standard deviations (3sigma) of the variation as a percentage of the average material removed ("3sigma percentage standard deviation"), and this will be referred to as 3sigmaPSD.
Click here to enlarge image Figure 3. Initial and final cleft depth for two feature sizes after SEP etching of ~12,500Å of as-deposited ECP copper. The degree of planarization (DoP) is given above the cleft depths. Error bars indicate ±1 standard deviation.
A four-point probe sheet-resistance measurement system from Creative Design Engineering Inc. (Model ResMap 168) was used for thickness measurement of copper and other conducting metals. An appropriate correction was made to eliminate the thickness effect on the bulk resistivity values. Radial maps with 49 points and 7mm edge exclusion were used for all measurements. Dielectric measurements were taken on a Rudolph FE-III ellipsometer using a 49-point radial map with a 3mm edge exclusion.
Click here to enlarge image Figure 4. Feature recess (dishing) before SEP (as-deposited ECP copper) and after SEP etching of 55% as a function of feature size. The upper bars show the degree of planarization. Error bars indicate ±1 standard deviation for their respective data sets.
Surface roughness, cleft depth, and recess measurements were performed on a KLA-Tencor HRP-220 high-resolution profiler. A stylus of 0.05µm radius was used for determining step-height measurements of all feature sizes.Blanket metal etch performance
The first tests on blanket wafers were performed to determine copper etch rates and post-etch surface roughness values. Etch rates in the range of 5000-20,000Å/min were possible using various chemistry mixes. All trials showed an improvement in surface-roughness compared to the as-deposited film. A preliminary target range of 10,000-15,000Å/min was selected to provide for reasonable process throughput while still allowing for accurate endpoint control. At this point, a chemistry was chosen ("Solution A"), and a set of processing parameters was selected ("SEP01") for all of the test data reported here. All process parameters were held constant with the exception of etch time for some tests.
Etch performance was determined by targeting the removal of approximately 55% (~8300Å) of the as-deposited 15,000Å copper thickness. The etch rates and 3sigmaPSD values for repetitive trials at the 55% removal point is given for both the electroplated and PVD copper wafers (Fig. 2). The average etch rate for the ECP copper wafers was 14,000Å/min with a standard deviation of 680Å/min. The average 3sigmaPSD was 9.17%. The etch rate and uniformity for blanket PVD copper is very similar to that of the electroplated copper and averaged 11,720Å/min with a standard deviation of 450Å/min. The 3sigmaPSD for the PVD wafers was 9.16%. A selectivity between electroplated copper and PVD copper of 1.13:1 was found. This selectivity near unity assists in controlling the SEP process at the boundary of the electroplated "bulk" and deposited "seed" layers of copper.
It is interesting that very low 3sigmaPSD nonuniformities (<5%) were achieved during some lower etch rate trials. Further development of the processing parameters is expected to yield sub-5% 3sigmaPSD results for etch rate recipes in the targeted range. In addition to uniformly etching across a wafer, the SEP process parameters can be varied to obtain either edge-fast or edge-slow etch performance. By varying SEP process parameters, a correction can be made for some concentrically nonuniform copper depositions.
One blanket tantalum wafer and one blanket tantalum nitride wafer were run with each of the first four pairs of ECP and PVD copper wafers processed with recipe "SEP01" and "Solution A." No measurable etching was noted for either the tantalum or tantalum nitride films, indicating a near-infinite selectivity of copper to either barrier film. For a multistep planarization process, this extremely high selectivity was the desired effect for "Solution A." Additional tests with thermal oxide also showed no measurable etch rates.
It is evident from the results of blanket copper wafers that some of the key technical goals that are necessary for the planarization of copper dual damascene structures have been achieved. A low 3sigmaPSD is an important requirement for the uniform clearing of copper on field areas as well as to avoid dishing across the wafer surface. Moreover, because of high selectivity of the etching solution, the barrier layer will remain intact and undamaged.
Planarization of patterned copper wafers
One set of wafers with superfilled ECP copper and one set of conformally deposited ECP copper wafers were used for patterned material tests (Fig. 1). Copper 14,000Å thick was electroplated on 1000Å of PVD Cu seed on 250Å of PVD TaN on 10,000Å of SiO2. The superfilled wafers contained 0.6µm-deep trenches, and the conformal wafers contained 0.8µm-deep trenches. The SiO2 was deposited by a plasma-enhanced tetraethyl orthosilicate process. The repeating test pattern contains various feature sizes and loading densities. These test wafers were supplied by Sematech.
The superfilling ECP process that preferentially deposits copper in the bottom of trenches leads to a final as-deposited surface that has more copper overfilling on top of trenches and less on dielectric spaces or field areas close to trenches. The cleft depth (or recess) of this technique of electroplating for the 1.50µm and 2.50µm features was approximately 3000Å.
Planarization results were evaluated at two stages. For the first stage, 85% of the total Cu thickness was removed. For the second stage, wafers were etched until the interface of the barrier metal layer was exposed. The planarization performance was evaluated by monitoring the change of feature recesses after each stage of spin-etch processing. The extent of planarization could then be described by a parameter defined as "degree of planarization," which is expressed by the formula:
DoP = 100(1 - Rf/Ri)
where DoP = degree of planarization (%); Ri = initial recess, before SEP (Å); and Rf = final recess, after SEP (Å).
Note that the term Rf is used as a descriptor for the spin-etch process, similar to dishing for the CMP process. A higher DoP value indicates that the depth of a recess has been significantly reduced, and a 100% value indicates that the recess has been completely eliminated.
The initial and final cleft depth for the 1.50µm and 2.50µm features is given, along with the degree of planarization (Fig. 3). At this stage, the recess was approximately 500Å for 1.50µm features and 800Å for 2.50µm features. The degree of planarization was about 80%. (The initial recess in these trench features was 3000Å.) A reduction of recess depth by about 2500Å with a removal of approximately 1.20µm of copper distinctly shows that the SEP process has a leveling effect and is not conformal. The high DoP value of 80% observed with 1.50µm and 2.50µm features indicates that the planarization is promising with the SEP process, even at an early stage of development. Two of the wafers were further processed to endpoint, and the final dishing of the 1.50µm and 2.50µm features was a 500Å protrusion and a 1200Å recess, respectively.
The small positive value for the 1.50µm feature indicates copper that is slightly above the field, while the negative value for the 2.50µm feature indicates a final recess below the field. The results indicate that the recesses at endpoint are higher than expected. We believe that because we have not yet optimized the endpoint parameters, the wafers received a longer than desired etch.
Click here to enlarge image Figure 5. Profilometry trace across a large field (2.50µm features with 0.50µm spacing) showing maintenance of dimensional integrity of the dielectric spaces and a lack of the erosion typical of other planarization methods.
In previous work on patterned wafers with near conformal plating [3], for feature sizes between 0.35µm and 0.50µm, the near-zero initial recess was maintained after SEP (Fig. 4). This was assigned a value of 100%. The DoP values for 1.00µm features were less than those obtained with the superfilled material. This comparison of the planarization behaviors of the wafer having different surface topographies shows that the surface topography of post-plated wafers has a strong influence on the degree of planarization that can be achieved. Future testing with wafers that are electroplated with newer pulse-plating techniques is expected to provide even more positive planarization results. Trench regions will once again be highly filled, but as opposed to superfilling, arrays of fine features (typically < 0.50µm) should not exhibit a large excess mound of copper (Fig. 4).The results obtained to date on local planarization of different feature sizes in the range of 0.35- 2.50µm for both conformal and superfilled copper plating, illustrate that the SEP process as presented here has an inherent planarization capability. This indicates that the process involves a higher etch rate at the projections and on field areas than at crevices or in recesses.
Absence of erosion effects
CMP of copper damascene structures can cause an unwanted removal of arrays of fine dielectric features (often referred to as erosion) and occurs due to the mechanical polishing of dielectrics by the pad. This even occurs with high-modulus materials such as dense SiO2. To evaluate the erosion effects for SEP, we measured the planarity of an array of fine lines after etching past the endpoint. A profilometry trace of an over-etched wafer across a 50µm-wide array of 2.50µm lines with 0.50µm spaces is shown in Fig. 5. The array has maintained its dimensional integrity after SEP without any erosion, even in an over-etched condition.
No dielectric removal (erosion) due to the current SEP chemistry has been measured. No dielectric removal was anticipated because the SEP chemistry was not designed to etch either barrier materials or dielectrics. It should be noted that planarization techniques dependent on mechanical contact can still remove these materials even though the chemistry is not designed to do so.
Conclusion
The etch rate and nonuniformity across the wafer can be controlled by varying the parameters of the SEP process to provide for reasonable processing times and high-quality results for both the electroplated Cu and PVD seed-Cu layers. The etch/planarization chemistry provides a smooth, final, copper surface and has a near infinite selectivity to tantalum and tantalum nitride barrier metals, as well as to conventional dielectric materials.
The SEP technique has demonstrated the inherent ability to completely planarize copper for a range of feature sizes from 0.35-0.50µm. SEP also provides a high degree of local planarization with feature sizes in the range of 1.0-2.50µm after removal of 85% of the copper thickness. No dielectric erosion was noted after planarization. Further development activity is underway to improve the current results as well as to allow for planarization of larger features in the 5-100µm range. Because the SEP process uses a production-proven platform, future developments can easily be integrated into the manufacturing environment.
Acknowledgments
The authors wish to acknowledge the management of Honeywell's Semiconductor Technology and Research Center and SEZ America for support in all development activities.
References
- D.C. Edelstein, "Advantages of Copper Interconnects," Proceedings of the 12th International IEEE VLSI Multilevel Interconnection Conference, p. 301, 1995.
- D.T. Price, R.J. Gutman, S.P. Murarka, Thin Solid Films, 308-309, pp. 523-528, 1997.
- J. Levert, S. Mukherjee, D. DeBear, "A Novel Spin-Etch Planarization Approach for Dual Damascene Copper Interconnects," ECS Conference, Hawaii, October 1999.
- J. Levert, S. Mukherjee, D. DeBear, "Spin-Etch Planarization Process for Copper Damascene Interconnects," Semicon Japan, December 1999.
Donald S. DeBear received his BS in electrical engineering from the University of California, Davis. He is an R&D process engineer specializing in frontside processes, including structuring, cleaning, film planarization, and post-etch residue removal at SEZ America Inc., 4828 So. 40th St., Phoenix, AZ 85040; ph 602/437-5050, fax 602/437-4949, e-mail [email protected].
Joseph A. Levert received his BS and MS in mechanical engineering from Tulane University and Arizona State University, respectively, and his PhD in mechanical engineering at the Georgia Institute of Technology. He is a senior engineer specializing in planarization and low-k dielectrics at Honeywell.
Shyama P. Mukherjee received his MS in metallurgy from Imperial College, London University, and his PhD in materials science from the University of Manchester, England. He is a senior planarization engineer specializing in planarization and low-k dielectrics at Honeywell.