Issue



Advanced R&D: CMOS: How far can it go?


03/01/2000







SPECIAL SECTION: EUROPEAN TECHNOLOGY

Simon Deleonibus,* LETI (CEA-GRENOBLE)
Département de Microélectronique, Grenoble, France

European research into the limits of CMOS technology, which comes from the demand for low voltage, low power and high performance, stems from strong cooperation between device and materials efforts. This cooperation is addressing the great challenges for engineering sub-100nm gate length devices, including gate-channel and substrate, source and drain, and gate dielectric engineering. In one example, engineers at LETI have achieved 20nm finished gate-length functional n-channel MOS devices.

It is clear in the 1999 International Technology Roadmap for Semiconductors (ITRS) that "showstoppers" for CMOS scaling will require special attention. In our research at LETI we are focusing on possible solutions that could lead to the required breakthroughs or evolution to enhance CMOS performance, especially in design. We are addressing the question: "How can we offer a second life to CMOS?"

Our efforts are embodied in France's PLATO (Plateforme Technologique Ouverte) Microélectronique du Futur program that is focusing on ultimate CMOS, technological breakthroughs for sub-100nm CMOS, and alternatives to CMOS devices.

The program projects include researchers from LETI, manufacturers in the French semiconductor industry, universities, and the French Centre National de la Recherche Scientifique (CNRS). Already, we have some notable results, including fabrication of a 20nm finished gate length n-channel direct tunneling mode MOSFET with a 1.2nm silicon dioxide gate insulator (Fig. 1).

Lowering supply voltage

Trends in electronics markets are dictating increasingly lower voltage and lower power dissipation. Standby leakage and active power dissipation will have to trade off with device performance without relaxing reliability. Indeed, the industry roadmap assumes that microelectronics is in the regime of a nearly constant field scaling since the introduction of <5V supply voltages. However, for sub-100nm devices, the following issues cannot be avoided:

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Direct tunneling through SiO2 occurs whenever thickness is <2.5nm. This increases the contribution of leakage in power consumption. Nevertheless, SiO2 operating in the direct tunneling current regime has been demonstrated to be usable down to a thickness of 1.4nm without affecting device reliability [2, 3].

High doping levels in the channel, reaching >5 x 1018 cm-3, enhance parasitic tunneling reverse current in sources and drains up to values of 1A/cm2 under 1V [4].

Classic small dimension effects are more severe than the fundamental limits of switching due to quantum fluctuations, energy equipartition (statistical mechanics), or thermal fluctuations. Thus, a minimum value of threshold voltage is related to:

  • subthreshold inversion that will increase leakage current up to a few nA/µm even for ideal fully depleted SOI (59.87 mV/dec at 300K) considering supply voltage of 0.50V. The limit VT value would then be 180mV, precluding supply voltage lower than 0.50V. Otherwise, the limit on leakage should be relaxed; and

  • short channel effect due to charge sharing along the transistor channel. This effect is the most severe and is strongly dependent on gate-channel coupling capacitance, junction depth, channel length, and doping concentration. This effect is the main limitation to a minimal design rule. It can be of the order of the threshold voltage itself [5] if low threshold voltage values are reached. We consider VT ~ VS/3 for <30% delay degradation [6].

Statistical dopant fluctuations are becoming increasingly important because the number of dopant atoms in the channel of a MOSFET decreases with scaling. Thus, random dopant placement in the volume of a MOSFET channel by ion implantation must be considered. Whether the distribution is binomial or Poissonnian [7-9], dopant fluctuations become very severe for geometries <50nm. Moreover, the discrete nature of dopant distribution can also give rise to device-characteristics asymmetry [9].

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Figure 1. Id vs. Vd characteristics for 25nm and 20nm gate length MOS transistors (the metallurgical channel length of the 20nm device was 4nm) [1].

Our work has focused on possible solutions to overcome the physical limitations the industry is likely to encounter in a classic scaling scenario through the different aspects of MOS device optimization, namely gate, channel, and substrate engineering; source and drain engineering; and gate dielectric engineering.

Gate, channel, substrate engineering

Gate-architecture engineering must be achieved together with the channel engineering, as both physical characteristics will affect the nominal threshold voltage value given by the well-known expression for nMOSFET:

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From this expression, VT depends on the gate material extraction potential as well as the doping concentration in the channel.

Classic scaling of bulk MOSFET

The management of low threshold voltage values will be achieved through several feats, for example, adjusting the gate insulator thickness (which we address later). It will also require tuning surface doping concentration as low as possible. Here, a retrograde profile is the conventional answer to achieving maximum bulk concentration, limiting punch-through efficiently, together with low surface concentration that maximizes mobility (reduction of scattering by dopants). It is easier to obtain low threshold voltage values required for low supply voltage. However, excellent localization of the dopant profile is needed to minimize, as much as possible, junction parasitic capacitance and body effect.

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Figure 2. Damascene metal gate based on sacrificial-gate architecture developed at LETI [16].

The use of heavy ions such as indium (In) for nMOSFETs and antimony for pMOSFETs has been suggested. Besides a defect annealing issue, the use of In suffers from the difficulty of carrier freeze-out [10] and activation of these impurities at a concentration higher than 1018 cm-3 because of the solubility limit of these atoms in silicon. Selective silicon epitaxy of the channel has also been suggested to achieve almost-ideal retrograde profiles [11]. Other solutions, such as strained SiGexCy-based alloy epitaxy, will increase the mobility in a buried heterojunction channel [12]. However, high quality gate insulator and subthreshold characteristic optimization require modifications of the device vertical structure and low thermal budget.

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These solutions will allow a new family of high-frequency, low-noise devices that will be needed for future high-volume telecommunications applications.

Future scaling will also require choosing the right gate material. Symmetry of threshold voltage for n and p channel devices (VTP = -VTN) makes it a challenge for low-voltage designs to achieve ideal transfer CMOS inverter characteristics (i.e., trade off between performance and standby leakage). Several alternatives have been envisaged.

Use of n+ poly gate for nMOSFET and p+ poly gate for pMOSFET theoretically allows threshold voltage adjustment by enhancement of the well dopant concentration. This solution suffers from many problems essentially related to boron penetration into SiO2 coming from the p+-doped gate; much has been published on this subject. Nitrided SiO2, deposited via numerous techniques, is a way to limit this effect without avoiding it. However, the creation of trapping centers in the oxide or at the SiO2-Si interface will decrease carrier mobility. Practically, gate depletion is preferred as a trade-off.

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With the use of midgap gate material, only one material is needed for n and p MOSFETs. However, the flat-band voltage is shifted by half the Si bandgap (i.e., 0.55eV). This results in too high an absolute value of VT if surface concentration is not compensated or reduced. Then, surface punch-through would be an issue. In this case, silicon epitaxy can also be used to achieve low surface concentration together with higher bulk concentration to limit punch-through (as with a polysilicon gate). Metal gate integration is not obvious, however, because the popularity of silicon gate technology is tied to the self-alignment of sources and drains to the gate. The process sequence has to be modified to allow a hot process after source and drain implantation for dopant activation.

Several approaches to such modification have been proposed. The classical process integration requires the protection of the metal gate material from ion implant and oxidation during the subsequent dopant-activation anneal. TiN is often chosen as a gate material [13] because it is usable as an Al barrier and a W adhesion layer. It is also popular because it allows the combination with Ta2O5 thanks to its chemical compatibility [14, 15].

Alternative approaches, such as the damascene gate (Fig. 2) [16] or replacement gate, have been proposed to avoid the source and drain integration problem. These solutions are ideally suited to integration with a high dielectric constant gate insulator [14]. Moreover, the damascene gate offers the possibility of multithreshold devices by allowing several gate materials on the same chip. High-frequency optimized devices together with standard CMOS could then be embedded on the same chip.

Silicon on insulator

Use of silicon on insulator (SOI) is another way to manage low threshold voltage. A fully depleted architecture can approach a 60mV/dec subthreshold slope using <30nm SOI films [17, 18]. Practically, ultrathin SOI films are so difficult to control that several reports propose partially depleted SOI [18, 19]. Unfortunately, the loss of the advantages of fully depleted devices cannot be totally compensated by using a dynamic threshold metal architecture (DTMOS) [19]. In addition, low power and RF applications are more easily manageable than with bulk technology. SOI material should enable the industry to realize advantageous devices such as double gated MOSFETs [20]. With these devices, short channel effects can be drastically reduced and high drivability can be obtained. Mastery of the fabrication process and scaling to small dimensions has to be shown, however.

Vertical transistors

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Vertical transistors were first used to study ultrasmall devices without the need for aggressive lithography. Now, we are seeing this technology successfully used in some commercial products — for example a fast read-only memory from Siemens [21] — that use RPCVD epitaxy. Prospective work is also being done for RF applications [22, 23].

Besides the need for integration capability, however, these approaches have to be improved because gate-to-source and gate-to-drain capacitance is still an important issue. In addition, the minimum transistor width is imposed by contact size. Vertical transistors cannot be universal, although they could be good candidates for niche applications.

Figure 3. Id vs. Vg for a) gallium pockets (GP) and b) indium pockets (IP) as defined in Table 3. Dotted lines correspond to 75nm devices, solid lines to 65nm. Gate width equals 10µm and Tox equals 2nm for all devices. (Source: Ref. 3)

Gate-dielectric engineering

Gate-dielectric engineering will have a great strategic impact upon integration of terabit-class devices. SiO2 could be used practically down to a 1.4nm thickness, corresponding to leakage of 1A/cm2, without device performance and reliability degradation [2]. A decrease in performance has been reported, however, if the gate oxide thickness is <1.3nm [24], suggesting a surface roughness limited mobility process due to the proximity of a sub-oxide. Still, the strong band bending due to quantum mechanical correction affects the lower limit of supply voltage in the constant field scaling approach [25]. Performance and subthreshold slope optimization will require a 1nm-range equivalent SiO2 thickness gate insulator for sub-0.5V supply voltage.

A lot of know-how on high-k dielectrics will come from DRAM device development. These solutions still require R&D for MOS applications, however, because a silicon-compatible buffer interface is needed. Furthermore, high-k materials have a smaller bandgap than SiO2, and hole trapping is a key reliability issue [26] (see Table 2). Before these materials are ready for use, silicon nitride could be an intermediate solution [27]. TiO2 [28] is also being given considerable attention.

Source-drain engineering

Most work in source-drain engineering is searching for a compromise between MOSFET access resistance and increasingly shallow junction depths. Salicidation is a necessity with dual Si-gate devices. However, a trade-off between source-drain sheet resistance and MOSFET access resistance must be found due to the dopant consumption during silicidation. Today, elevated source-drain structures are still a research topic due to the critical nature of prebake before selective epitaxy. Extension halo pocket implants are very helpful to clamp the device punch-through and reduce the short channel effect. Heavy ions are very useful to limit the short channel effect as well as junction parasitic capacitance, along with offering good reliability [3] down to 50nm geometries (see Table 3 and Figs. 3 and 4).

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Figure 4. VT vs. Lg at Vd = 50mV for classic (CA), gallium pockets (GP) and indium pockets (IP) as defined in Table 3. (Source: Ref. 3)In general, the use of pockets can relax the constraint on gate oxide thickness scaling, resulting in better control of the short channel effect and DIBL (see Fig. 4). Low energy (<1keV) [24] and heavy molecules (BF3) [29], B10H14 [30], etc., could be the easiest ways to replace boron to achieve p+ shallow junctions. Plasma doping is being investigated as a possible alternative to obtain <25nm as implanted p+ junction depths [31]. However, transient enhanced diffusion (TED) is still the limiting process to reach the specified values as final junction depths.

Interconnects?

Interconnect technology is probably the toughest subject, and the most uncertain area, for future IC development. The main difficulty is combining materials science and equipment development for manufacturing needs. Copper integration is widely accepted as a replacement for aluminum, combined with low-k dielectrics. For high-speed design, a trade-off has to be realized between the number of interconnect levels and manufacturing cost [32]. The reduction of electromagnetic parasitics [33] and heat dissipation in low-k dielectrics are new issues to address. Research is needed on other approaches such as local and chipscale optical interconnects.

Evolution or revolution?

Will there be any alternative devices available to replace CMOS? That is the scope of today's efforts that various research teams in Japan (Hitachi, Toshiba, NTT, etc.), US (U. Minnesota, U. NY), and Europe (Fasem project) are making on single-electron transistor (SET) devices [34]. No solution has been found yet, however, that can replace CMOS devices in a straightforward manner. Some teams have noted the possibility of achieving memory functional devices using Coulomb blockade effects. This effect supposes that the Coulomb energy (i.e., e2/2C) might be much larger than the thermal energy of electrons (kT). This energy is needed to localize electrons in a Coulomb barrier, provided that tunneling is the limiting process. Implicitly, we have to use very low capacitance and sufficiently high tunneling resistance. On the other hand, the Coulomb blockade process will be self-limiting by charge repulsion. That means we have to admit a low speed charge transfer process. The "staircase-like" current voltage characteristics makes these devices attractive for memory applications [35]. No satisfactory solution has been found for logic devices, however [36].

Conclusion

Today, the demand for low voltage, low power, and high performance are the great challenge for nanoelectronics device engineering. The various possible solutions will come from properly addressing gate-channel and substrate, source and drain, and gate-dielectric engineering. The most strategic issues, other than lithography and interconnect technology, will be low-voltage supply management and the necessary gate dielectric engineering in the range of sub-1nm equivalent oxide thickness.

Historically, innovations in this industry have come from cooperation among device and materials researchers. Accordingly, the PLATO initiative in France and EURACCESS initiative in Europe are able to offer an access to state-of-the-art facilities and equipment through a network of hubs and laboratories exchanging wafers. This initiative could be a beginning for multipartner, multicultural approaches to advanced R&D for nanoelectronic devices.

Acknowledgments

Additional authors include Christian Caillat, Jacques Gautier, Georges Guegan, Michel Heitzmann, François Martin, and Serge Tedesco, who are all with LETI Département de Microélectronique, Grenoble, France.

This work has been carried out with PLATO Organization teams and tools within the framework of the Ultimate CMOS project. Some of the work discussed here was presented at the ESSDER Conference 1999 in Leuven [37].

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Simon Deleonibus obtained his PhD from Paris University. With LETI since 1986, he is the manager of the silicon nanoelectronics device integration group and the ultimate CMOS project in PLATO. LETI (CEA-GRENOBLE) Département de Microélectronique, 17 rue des Martyrs, 38054 Grenoble, Cedex 09, France; ph 33/0/476-88-59-73, fax 33/0/476-88-54-59, e-mail [email protected].