Advent of SOCs thwarted: Panelists cite packaging standards testing costs

02/01/2000

The move to the next level of system-on-a-chip (SOC) designs is being thwarted by major problems in the complexity and costs of testing, according to a panel of European executives at the Productronica exhibition in Munich, Germany.

They also cited a lack of standards for a plethora of advanced packaging schemes using flip chip and chip-scale form factors. This discourages development of suitable automated machinery. The evening session was organized by Semi and included executives from chipmakers as well as test system and packaging firms.

Test problems have actually led some end-users to abandon SOC projects and stay with multi-chip solutions, according to Gene Gretchen, back-end VP and general director for STMicroelectronics.

"Test may be up to 20% of total cost," stated Gerhard Kessler, senior managing director of Advantest, citing a need for greater productivity in testing. All segments of the design/manufacturing cycle need to gain what he calls a "holistic test competence," including chip designers, test equipment vendors, designers of test handlers, and manufacturing specialists. He cited chip test requirements for the automotive market as an example, saying they have reached levels the military required five years ago. Also, chip speeds are rising rapidly and test probes are not designed to handle the frequencies that will be required.

Gretchen of STMicroelectronics agreed. "The cost of test is now equal to or even greater than assembly, and this is not acceptable," he said. As a result, test costs can jeopardize the future of SOCs by negating their advantages.

"As complexity is added to the chip, test costs rise exponentially, not linearly," Gretchen explained. The chip may be testable, but it is proving very difficult to do the job in reasonable time at an affordable cost. Tester vendors need to have better input from chip designers and fabs about what is really required, he suggested, citing the secrecy that often surrounds advanced chip design projects. An SOC that will only run on the line for six months can't justify the cost of a megatester, Gretchen said, adding that test systems need to be scalable. One approach might be to pay only for the options actually needed, or, alternatively, the equipment might be dynamically reconfigurable to match the testing needs of different chips.

"To test an SOC, we will need a 'tester-on-a-chip' using the same hardware and software," suggested Pascal Ronde, GM of Agilent, the test company spun off by Hewlett-Packard. He agreed that scalable platforms will be needed to handle both low-end and high-end designs. Testing issues could also be addressed in SOC designs, he suggested. Exactly replicating cells and software over the chip can help, and consistent standards are needed for software and packaging. Memory test might be aided by surrounding memory with buses. He cited flash memory, which is designed to allow back end testing to be combined with wafer sort. It is much more efficient, he said, to test "strips" of circuitry which all look the same.

More "site synergy" will be needed to accomplish the coordination needed to make the SOC concept work, according to Steven Lerner, CEO of CS2, a packaging foundry in Belgium. When Volkswagen builds a plant, he explained, "all the suppliers huddle together to meet the customer's needs." The same may happen in electronics, he believes, instead of spreading different operations all over the globe. SOC projects may require a service coordinator, who can help link chip designers, test, packaging, and manufacturing. While Asia may offer a 50% wage advantage, Lerner says labor is only 15-20% of total cost, and only 8% in his loaded cost models, with materials and equipment depreciation now becoming predominant. "It isn't worth putting a plant in Asia for a 4% cost delta," he said.

Another problem faced by test system vendors is the different concepts of an SOC in different areas of the world, according to Hans Giessibl, VP sales support, SZ Test Systems. In the US, it includes a CPU, DRAM, and ROM, and in Asia it may be a CPU and DRAM, while in Europe it is more likely to include analog circuitry, and even high power and high voltage. Scalable systems can provide some flexibility, but it is important to use the same software. For mixed signals, designers need to focus on parallel structures and they need to work closely with packaging vendors.

In advanced packaging, there is no clear trend in wafer scale and chip scale, or micro-BGA, technologies, according to STM's Gretchen, because there are too many divergent needs and constraints. There probably never will be a niche package for SOCs, he feels, although a number of chip scale solutions should survive in large volumes.

The second emerging area is ball grid arrays, or BGA packaging, which is leading toward SOCs. Current standard packages, like TQFP, go only up to about 208 contacts, and more than 200 contacts are needed for many complex chips, not just for I/O, but for testing access.

There is a strong increase in demand for bumping technology in Asia, particularly in Taiwan, but also in Japan, according to Franz Richter, CEO, Suss Microtech. He pointed out that front-end processes, such as spin-coating, are now being applied to meet advanced packaging needs. He stressed that industry must work closely with research institutes to push the technology forward. Standards are critical, he said, so that machinery can be sold without excessive customer support.

Packaging equipment suppliers need better feedback from customers, on issues such as when copper will really come and when it will be in high volume, according to Jurgen Steinbichler, wire-bonding manager for ESEC. There needs to be close interface between the front and back ends of manufacturing, and vendors need to develop fine-wire bonding solutions in collaboration with customers, he indicated.

The community of users wants standardization of chip scale packaging, indicated Ehle Zahel, CEO of PacTech. "There is too much variety," she said. She expects to see some mainstream technologies emerge, and she suggested that bumping and CSP can be linked. "They are not contradictory," she said, "there can be wafer-level CSP with bumping for next generation packaging, even though wire-bonding will be dominant for some time."

This needs to be developed for both integrated device manufacturers (IDMs) and subcontractors in the future. But it is essential that there be packaging companies in Europe, she said. Europe has the best resources for developing advanced packaging, and there needs to be synergy between chipmakers and near-by packaging and test companies.

Nonstandard packages are creating big problems for testing, according to Kessler of Advantest, because of the difficulty of developing adequate interface technology. He also pointed out that test probe card technology needs to be improved. Chip yield depends on the characteristics of probe cards, and the RF characteristics of pins are falling behind testing needs. — B.H.