1999 ITRS: 2000 begins with a revised industry
01/01/2000
Pieter "Pete" Burggraaf, Senior Technical Editor
Three changes jump out of the International Technology Roadmap for Semiconductors 1999 Edition — "international" in the title, a transition back to a less aggressive three-year technology-node cycle, and a "red-box" wall for conventional CMOS technology beyond the 100nm technology node in 2005.
Sponsored by the Semiconductor Industry Association (SIA) and published by Sematech, the International Technology Roadmap for Semiconductors (ITRS) 1999 Edition was produced in cooperation with a host of organizations: the European Electronic Component Manufacturers Association, the Electronics Industries Association of Japan, the Korea Semiconductor Industry Association, the Taiwan Semiconductor Industry Association, and the Semiconductor Research Corporation. Although an international roadmap has been referenced since 1998, the 1998 ITRS update was an interim document in which the Roadmap's infamous tables — labeled "solutions exist" (white boxes in tables), "solutions being pursued" (yellow), and "no known solutions" (red) — were revised without the explanatory text found in a complete edition.
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Paolo Gargini, Intel director of technology strategy and Roadmap committee chair, tells Solid State Technology, "It became obvious that the 10-to-15-year projections of the 1992, 1994 and 1997 editions were important sources of information for semiconductor industry equipment and materials suppliers, and to researchers addressing major limitations. But we received comments on specific points that revealed national and regional variations in technology needs." For example, a general criticism of the 1997 Roadmap was that chip sizes were forecast to be much larger than most experts thought. "The simple fact is that a US-based Roadmap was creating some strain in an industry where suppliers are global," says Gargini. In addition, an international roadmap was dictated because, increasingly, semiconductor manufacturers are forming partnerships, alliances, and consortia that further blur regional distinctions of process technology.
Three-year cycles?
Significantly, Roadmap authors have not projected a clean continuation of the industry's blistering 2-year/technology node pace since 1995 (i.e., 0.35µm in 1995, 0.25µm in 1997, and 180nm in 1999). Gargini says, "These were exceptional years and the pace is unlikely to be completely sustainable as we move forward."
The authors have also modified previous definitions of technology nodes, which had been defined by just DRAM ½ pitch and MPU gate lengths. As Table 1 shows, the 1999 ITRS now lists DRAM ½ pitch, MPU gate length, MPU-ASIC ½ pitch, and ASIC gate length in defining technology nodes. In addition, the links between IC parameter definitions have changed. For example, where the previous Roadmap identified 130nm DRAM ½ pitch and 100nm MPU gate lengths as the 130nm technology node, the 1999 ITRS redefines this node with 130nm DRAM ½ pitch and 85nm MPU gate lengths, showing that MPU gate dimensions are not rigidly linked to DRAM half pitch and are, in fact, scaling more rapidly.
With more detailed node definitions, the classic DRAM ½ pitch technology node sequence (i.e., 180, 130, 100, 70, etc.) and years are now muddled with many more interim nodes added to capture different scaling rates. However, transition back to a three-year cycle between nodes is anticipated in the year 2005, when devices with 100nm DRAM ½ pitch and 65nm MPU gate lengths should emerge.
Lithography
Lithography economics and materials technologies are major factors in the switch back to a slower three-year cycle. The two-year cycle was fueled by the relatively easy transition from i-line to 248nm deep-UV lithography. Today's view is that either 193nm or phase-shifted 248nm will be able to produce 100nm MPU gate lengths in 2001 and possibly 130nm DRAM 1/2 pitch features in 2002. Beyond this, more data is needed. Gargini says, "If improvements in optical lithography continue to surprise us, a post-optical technology may not arrive until the 70nm node in 2008 and perhaps not even until the 50nm node in 2011."
While lithography's progress was the hot topic in the interim between the 1997 and 1999 Roadmaps, particularly with the re-entry of 157nm optical technology, Mark Melliar-Smith, president and CEO of Sematech, says, "Today, I don't think the lithography challenges for the industry are the worst we have. Rather than lithography capability, today challenges are about cost-effective lithography — keeping costs down." The concern is making the right decisions about next-generation lithography (NGL) and making it fit into design cycle nodes, whether two or three years, and making sure that equipment and resist suppliers behind NGL get their appropriate economic reward.
"Other than lithography, over the next decade we are going to see some pretty nonincremental changes in technology for semiconductor manufacturing. Not the least of these will be significant changes in the gate stack — the way that the field effect transistor is actually manufactured," says Smith.
The red-box wall!
The 1999 ITRS tables, for the first time, are clearly divided to define "near term" (i.e., to the 100nm node and 2005) and "long term" (i.e., beyond the 100nm node) technology needs. It is the long-term set of tables that seemingly appear as a "red-box" wall for conventional CMOS technology (e.g., Table 2). Gargini says, "For the next five years, we see no limitations, but beyond that there are formidable obstacles to the industry's classically silicon, silicon dioxide, polysilicon scaling approach to continuously improve performance. The Roadmap shows that beyond 2005 we have to deal with replacing the gate oxide and the dual-doped polysilicon gate electrode, two of the industry's key technologies that go back to the 1960s." He stresses, "This doesn't mean the end of the industry, however. It is simply the end of the present scaling approach. While the industry will likely change some of the basic ingredients in the underlying IC technology, IC designers will likely not even know what we are doing."
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In essence, the "grand challenge" of the industry's roadmap has changed from ramping up to "copper, low-k dielectric, dual damascene" to "moving beyond the silicon dioxide dual-doped polysilicon gate stack era." In addition, while challenges are associated with introductions of new high-k dielectric materials and metal electrodes for DRAM storage capacitors, it is unlikely that one high-k dielectric and electrode materials combination will be suitable for both DRAM storage capacitors and MOSFET gate-stack structures.
Implied in this ITRS "grand challenge" is that CMOS gate stack changes of this magnitude normally require 10 years or more to develop and implement. The ITRS notes, however, that "there is much reason for optimism. Many promising candidate materials have been identified and some preliminary prototype MOSFETs have been produced, and several promising DRAM storage capacitor configuration have been identified." The ITRS caveat is that "production deployment requires the comprehension and solution of many difficult challenges that will require extensive resources to achieve production readiness. The grand challenge is not the eventual solution to these problems, but the marshalling of the appropriate industry and university resources required to meet the ITRS timeline."
Doping technology
The ITRS progression for scaled doped junction depths and gate stacks provides clear explanation of the grand challenge timeline. For the near term, doping technology is driven by the aggressive scaling of MPU transistors. What directly affects doping technology is more aggressive drive current (i.e., nominal Ion) specification for these devices, a ~25% increase on the 1999 ITRS, from 600 to 750µA/µm for n-channel and 280 to 350 µA/µm for p-channel devices. Walter Class, director of strategic marketing at Eaton Semiconductor Equipment Operations and 1999 ITRS front-end process technical working group chair, tells Solid State Technology, "The combination of more aggressive MPU gate length scaling and new drive current requirements has had a significant effect on near-term doping expectations. These force greater emphasis in understanding and minimizing all sources of parasitic resistance associated with CMOS source-drain regions."
ITRS source-drain extension junction depths have been decreased 5-10% and there is an added requirement for sheet resistivity of source-drain extension dopant regions. Class explains, "The doping process challenge directly related to higher Ion is achieving maximum dopant activation in the extension while achieving an abrupt dopant concentration change, both in depth and laterally." On the equipment side, this calls for very low energy (i.e., sub-KeV) ion implantation and spike annealing via enhanced traditional thermal or laser, microwave, electron beam, or another inventive technology.
The more aggressive values of Ion also mean ITRS is projecting a faster increase in gate capacitance with an associated thinning of gate oxides, before the transition to high-k gate dielectric material. For example, previously specified 1.3-3nm equivalent oxide thickness at the 100nm node in 2006 is now specified at 1.0-1.5nm in 2005. "This is a big change," says Class, "and means that there is a high probability that a high-k material, dual-metal combination will have to be introduced at the 100nm node."
Adding to the complexity, Class adds, "In the interim before conversion to dual-metal CMOS electrodes, there are significant near-term challenges associated with the level of active doping in the traditional dual-doped polysilicon electrode, leading to a new ITRS specification." This requirement arises because electrical depletion of dual-doped polysilicon electrodes decreases effective gate capacitance, thereby bringing forward the time when a high-k gate dielectric material would be required. This specification shows active polysilicon doping rising from 2.2 x 1020 percent active dopant atoms to a red box value of 4.6 x 1020 at the 100nm node, which exceeds solubility. "The challenge will be to achieve metastable dopant activation levels in polysilicon, or to deploy dual-doped polycrystalline silicon-germanium alloy, which has higher boron solubility."
The interconnect route
For interconnect technology, near-term challenges on the 1999 ITRS involve managing the rapid rate of materials introductions associated with dual damascene technology and its continued transition from aluminum to copper. In the long term, interconnect also shows that even with materials innovation traditional scaling will no longer satisfy performance requirements.
Christopher Case, chief technology officer at BOC Edwards and chair of the ITRS interconnect committee, tells Solid State Technology, "Introduction of progressively lower-k dielectrics, CVD metal, barrier, and seed layers, and additional elements for system on a chip (SoC) applications, provide significant process and process integration challenges. Interfaces, contamination, adhesion, mechanical stability, electrical parametrics, and thermal budget, compounded by more wiring levels for interconnect, ground planes, and passive elements, create a complexity that is difficult to manage."
The ITRS shows damascene processing flows dominating fabrication methodologies. While current copper damascene processes use physical vapor deposited (PVD) Ta-based barriers and Cu nucleation layers, continued scaling of features requires development of other materials and seed-deposition solutions by 2002. Bob Havemann, program manager for Cu/low-k integration at International Sematech and ITRS interconnect co-chair, says, "The transition from PVD to CVD is driven by the need for thin barriers with high integrity. As dimensions shrink, classic PVD metal deposition profiles tend to close off tops of features and complicate subsequent electrochemical deposition (ECD). It is anticipated that conformal CVD barriers will be required at 100nm. Porous low-k materials at 100nm also tend to have a rough surface inside the trench and via so a conformal barrier provides better integrity than PVD."
According to the roadmap, continuous improvement of tools and chemistries will extend electrochemically deposited Cu to 100nm and beyond, but small, high-aspect-ratio features necessitate simultaneous development and subsequent selection of alternative filling techniques. A thin barrier is also needed to maintain the effective conductor resistivity in these features. Further requirements include nucleation layer conformality that is more stringent to enable Cu ECD filling of damascene features. Havemann says, "Surface segregated, CVD, and dielectric barriers represent intermediate potential solutions, but by 2008 zero thickness barriers are required to maintain effective resistivity of the wire as we scale. If barrier thickness remains constant with scaling, then more percentage of the wire area will include a high-resistivity barrier material and performance will suffer."
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Near-term dielectric "management" needs include lower-permittivity materials for wire insulators and etch stops, and higher-permittivity materials for de-coupling capacitors and materials with high remnant polarization for ferroelectric memories. "The thermal, mechanical and electrical properties of these new materials present a formidable challenge for process integration," he says.
The ITRS foresees that aluminum wiring will continue in many MPU applications through 2003. For DRAM, low-k dielectric materials will be introduced at 130nm followed by copper at 100nm. Here the caveat is that this introduction is DRAM pricing sensitive. Havemann says, "DRAM's adoption of Cu will be driven by pattern and etch difficulty. Pattern and etch of oxide damascene structures provide better linewidth control, along with the cost advantage of the dual damascene process." He cautions, however, that it is hard to predict Cu implementation industry-wide, because it is tied to 300mm conversion — "a kind of double risk."
New with the 1999 ITRS, interconnect technology is defined for memory, microprocessors, and SoC product lines, the latter adding levels of conductors and dielectrics for the integration of resistors, inductors, capacitors and other SoC elements. Separate tables were added for SoC because timing and requirements differ significantly from MPUs. Havemann says, "SoC is meant to encompass ASICs that are less sensitive to performance, but more sensitive to functional density and cost."
Conclusion
The 1999 ITRS's look into the future reveals that many known semiconductor manufacturing technological capabilities are approaching limits. Adequate preparation as we approach this red box wall requires the investigation and development of a set of new devices usable beyond the limits of CMOS. Crucially, it cannot be the task of any single company to support the progressively increasing R&D investments that the industry faces. Indeed, the ITRS calls for "shared contribution in the pre-competitive domain."
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Pieter "Pete" Burggraaf has 25 years of experience in the semiconductor industry, including work at Motorola, Siemens, and ASM. He can be reached at 875 S. Yucca Drive, Wickenburg, AZ 85390; ph 520/684-1265, fax 520/441-3139, e-mail [email protected].
1999 ITRS metrology
On reading the 1999 ITRS, it is increasingly clear that the concept of in situ metrology will play out as "integrated metrology." International Sematech senior fellow Alan Diebold, chair of the US metrology technology working group, says, "This means getting metrology completely incorporated into the fab either as a cluster tool station or enabling process tools to use information from inline metrology more directly. The integrated metrology approach has been assumed by process tool suppliers."
The ITRS labels metrology among its "crosscut" concerns because it is key to so many processing efforts:
Lithography metrology. The loss of depth of focus (DOF) with increasing resolution of low-voltage scanning electron microscopy (SEM) technology is a concern for lithography's future. Diebold says, "Everything that we know now says that it won't be possible to maintain CD-SEM DOF when we start looking at 70nm and beyond." Among the proposed solutions is electron holography.
There is also a need for improved modeling that relates CD-SEM imaging to actual features. "Here, porous low-k materials are largely untested and may be difficult to measure by CD-SEM," says Diebold.
Overlay measurements will become increasingly difficult because of CMP and damascene processing, and the associated new materials. Traditional box-in-box targets will not capture all the errors possible, particularly those associated with changing focus with phase-shifting mask technology. "Adding to the complexity is the fact that getting a lot of information is difficult because these processes are proprietary to the IC manufacturers," Diebold says.
Very significant in the 1999 ITRS, the requirements for mask metrology are greatly expanded to include 20 different parameters, including mask CDs of isolated and dense line on the mask.
FEP metrology. Many of the challenges in metrology for front-end processing (FEP) revolve around measurement precision of very thin gate dielectrics and, eventually, high-k gate dielectrics. Here, where perhaps a future dielectric process will dictate maintaining vacuum between clean and deposition, is a good example of where integrated metrology may be required on cluster tools.
There is also an ongoing need for measuring very shallow implants and 2D and 3D doping profiles. "While SIMS will continue to play a role, extension of existing four-point probe, optically modulated reflectance, optical densiometry, and some newly introduced technologies need to be explored," says Diebold. However, the spatial resolution needed for these measurements seems beyond any existing technology.
FEP metrology now includes the requirement for capacitor dielectric measurement, and increasingly FEP and interconnect will be concerned with the measurement of interface properties (i.e., thickness and composition). "This will involve measuring very thin areas below the main gate dielectric," says Diebold. Perhaps this is best illustrated by the progression of interconnect layers. "Metal barrier layers for copper are getting so thin that the last three technology generations on the Roadmap replace a deposited barrier layer with a reacted barrier layer, i.e., either the low-k dielectric develops a skin, or copper is deposited to prevent diffusion or reaction with the low-k material. This whole concept comes down to making a difficult interfacial measurement."
Interconnect metrology. One of the challenges associated with interconnect involves ultimately measuring barrier and copper layers on patterned structures, in trenches and contacts, because the deposition is not exactly the same inside those structures as it is on a test wafer. Perhaps this need can be met by advancing today's acoustic or x-ray measurement technologies or by measuring an array of identical features.
In addition, interconnect metrology will require measurement of porous low-k dielectric films. "There has been a lot of work to measure the physical properties of these films, but in-line process control is going to be difficult because you need to make sure you have the right film thickness, you may need to measure pore size, and you need to determine water content," says Diebold. In-line IR ellipsometry measurements for low-k materials are under development. High-frequency measurement of low-k materials needs additional development to meet higher frequency requirements at the end of the Roadmap.
Materials, contamination characterization. Contamination and materials characterization continues to be a very important part of crosscut metrology needs, where new technologies will probably play key roles. "Micro calorimeter EDS is a high-resolution method that can be used for analysis of smaller particles on whole-wafer-based SEM defect review tools. In addition, for materials characterization, x-ray reflectivity will provide a very good means of getting film thickness for barrier layers. Scanning TEM (STEM) equipped with high angle annular dark field detectors, which is just becoming widely available, should prove valuable in measuring interfacial layer properties. STEM is very important and is providing support for developing new materials for FEP and interconnect."
The ITRS has also added a new section on processes reaching their statistical limits. "For the long term, we need to be concerned with controlling a process when the process itself has a large statistical variation. Consider, for example, doping in the gate area of a transistor where there may be just a few dopant atoms across the length of the gate and transistor threshold voltages might be affected," Diebold says.
1999 packaging roadmap
Packaging technologists will see that the assembly and packaging (AP) section of the 1999 ITRS has definitely benefited from international cooperation. Bob Werner, director of advanced technology at International Sematech and chair of the packaging technology working group, says, "We brought together experts spanning consumer to high-end product market segments, and thereby realized a comprehensive view of worldwide AP requirements." Werner's group took a systems-level approach to packaging, from a chip carrier down to its impact on the printed wiring board. The ITRS now includes an extensive section on interconnectability and wirability of the chip carrier and its ability to distribute power ground and signal from the chip to the chip carrier to the board.
The Roadmap also includes an expanded discussion of wafer level packaging. Here, the alignment of flip-chip bump-pitch scaling to progressive technology nodes has been split into two IC categories. Werner says, "It became obvious that for large chips with ample bump area we could preclude the need to drive bump pitch below 150µm. But with small chips where wire bonding is still competitive and bonding pitch is continuing to <70µm, we are continuing to scale bump pitches along with the nodes."
Another expanded area covers chip contact reliability. "We wanted to address concerns as the industry continues to increase chip power and lower voltage. Increased currents and demand for more pads for voltage and ground means we must understand physical limitations," says Werner. The 1999 ITRS also more fully elaborates on chip-to-package thermal management challenges.
A major packaging challenge in the next five years will be the identification and solution of wire bonding and flip chip issues with increased use of copper and low-k materials. Among the issues are bonding gold to copper and thermal and pressure issues related to bonding with relatively soft underlying low-k materials. "We need to watch for any potential delamination or reliability issues here," says Werner, "and to fully understand the interfaces involved."
To the credit of the international participation behind the 1999 ITRS, it reflects some significant changes in AP cost trends. "Widespread use of plastic ball grid arrays (BGAs) has created cost pressure on quad flat packs and ceramic BGAs. Some cost projections have gone down by 20-30% from the 1997 Roadmap."
Finally, qualitative analysis of system-on-a-chip (SoC) packaging requirements is a new part of the roadmap. Chi Shih Chang, senior fellow at International Sematech, says, "It's going to be challenging to design the required analog-to-digital technologies into the package, particularly power distribution management — preventing noise coupling between the digital and analog circuits." The SoC section will evolve quantitatively as the ITRS is expanded in subsequent validation phases.