Fab Automation: Fab-wide automation is critical to microelectronics' future

01/01/2000

Robert Helms, Texas Instruments, Dallas, Texas

Special Section - Technology Outlook

Significantly better productivity and improved cycle times are two aspects of our vision for the future of semiconductor manufacturing. "Significantly better" really means a "quantum leap" in cycle times and manufacturing productivity, driven by fab automation and other improvements. Why? Lower costs are a must and microelectronics product life cycles are already <12 months in many markets. Focus on this scenario will assure continued growth and acceleration for the IC industry.

At Texas Instruments, we have executed an accelerated technology development schedule over the last four years. In 1995, we lagged the leading edge by up to two years. In 1999, by some measures (e.g., SRAM cell size for embedded DSP applications), we are as much as six months ahead of the nearest competitor. This has allowed us to deliver an average 70% shrink every year over this period, providing an enormous benefit to our customers in the form of performance enhancements and cost reductions.

Continuing to provide these productivity improvements at the needed pace is a major challenge. According to the plan of the revised 1999 International Technology Roadmap for Semiconductors (ITRS), the trend is a drift back to three-year cycles/70% shrink. The industry's conversion to 300mm wafers has slipped by one to two years, driven by 200mm overcapacity, immaturity of 300mm equipment and process technologies, and the industry's downturn in 1998. These factors have made staying on the historical semiconductor productivity curve all the more difficult.

We are focusing on three factors to close the gap and drive us into the future:

• remaining on a 70% shrink path every two years, much as Intel has indicated [1];
• converting our remaining 150mm capacity to 200mm and moving new fabs to 300mm wafers on the most aggressive schedule possible; and
• increasing overall manufacturing productivity with faster cycle times, better equipment utilization, and faster yield ramps.

Factory flexibility

Faster cycle times, better equipment utilization, and faster yield ramps dictate a flexible factory with small batch sizes and fab-wide automation. For an automated 300mm factory running ASIC product, the concept of a single-wafer batch size can even make sense [2]. This is not new; many of the concepts were developed more than 10 years ago. At TI, for example, 1990 was the heyday of a single-wafer R&D program known as MMST (Microelectronics Manufacturing Science and Technology), which was funded by DARPA and the USAF to focus on automated flexible manufacturing. Toward the end of that program, program manager Bob Doering predicted, "100% single-wafer processing is now technically feasible. By the end of the 1990s, it should be possible for virtually all semiconductor manufacturing, even for large-volume commodity circuits produced on 300mm wafers." I believe this program still holds the world's record for the shortest processing cycle time of a complex part - six hr/mask level.

The transition to single-wafer processing is not happening overnight, but it was already 60% complete in 1993 at the close of the MMST program. As the industry continues to move to more single-wafer processing, cycle times will continue to decrease. At TI's joint R&D-Production facility in the Kilby Center, we are executing better than 18 hr/mask level for 25-wafer lots. For a fully automated fab configured to process single-wafer lots, six hr/mask level is well within reach.

300mm production, automation

Despite continued debate, 300mm production is here; 2002 will see no fewer than four 300mm factories in large-scale production, including TI. Interconnects will be all copper and critical levels will require 193nm lithography. Full automation will be a key foundation for all 300mm factories; this is a critical enabler for single-wafer lot processing. So, we end up with a win-win situation - reduced cost/unit area via 300mm and increased flexibility and reduced cycle time via fully automated processing.

Unfortunately, even 300mm and single-wafer lots are not enough to keep us on the industry's blistering cost-reduction path. Rapid shrinks are still necessary. At TI, we will continue to shrink by 70% every two years, at least through 2003. As the semiconductor recovery continues, especially for DRAMs, we believe others will return to a two-year cycle. If next-generation lithography technologies become available, we will be able to continue the two-year cycle beyond 2003. Rapid equipment change-outs necessary for these advancements not only require full automation, but also complete tool isolation; the factory cannot be perturbed by the installation of this new equipment!

Who will be capable of continuing the rate of capital investment necessary to remain at the leading edge of semiconductor manufacturing? Many believe that vertically integrated device manufacturers (IDMs) will choose to outsource to foundries. Indeed, consolidation will continue with more companies going fabless, leading to significant growth in foundries. However, some of this consolidation will continue by mergers and acquisitions within existing large IDMs. We at TI are convinced that process technology is a competitive weapon and we know that other large IDMs agree.

The 2000 landscape

We see the landscape of semiconductor manufacturing changing over the next 10 years. There will be fewer IDMs and more foundries, but they will have much in common. The winners of the next decade will have fully automated, 300mm factories, with isolated equipment. We will be printing sub-0.1µm features with new gate and interconnect dielectric materials. Hot lot cycle times through the fab will be less than one week. While a number of developments are required to make this a reality, robust fab-wide automation is critical.

References

1. WaferNews,Vol. 6.38, September 27, 1999.
2. For most products, a complete product run on a single wafer is not practical. Design and mask costs typically make the cost prohibitive. The flexibility to run single-wafer lots can, however, provide significant advantages for prototyping, debugging, and yield learning; short cycle times result.

Robert Helms received his PhD in electrical engineering from Stanford University, where he is also professor emeritus. He is VP and director of silicon technology research at Texas Instruments, PO Box 650311, MS 3700, Dallas, TX 75265; ph 972/995-6600, fax 972/995-6383, e-mail [email protected].