Materials: Silicon-pulling technology for 2000+
01/01/2000
Kyong-Min Kim, LG Siltron and KMK Associates, St. Charles, Missouri
Czochralski silicon-crystal-growth development work targets the alleviation of crystal-originated particles in silicon wafers that adversely affect IC yield and performance. One approach avoids void formation in situ; another forms small voids with a fast-pulling technique followed by an anneal of polished wafers to achieve avoid-free denuded zone. In addition, cusp magnetic Czochralski technology will continue to provide control of required oxygen levels with good radial uniformity.
As 2000 unfolds, we will see 300mm Czochralski (CZ) wafers being phased in for IC fabrication, picking up from the delay dictated by the past slowdown in the semiconductor industry. The use of 300mm wafers will approximately equal that of 200mm wafers about 2008, according to modelling from Sematech.
Today, most polished CZ wafers are used for MOSFET devices such as DRAMs; most epitaxial (epi) wafers (i.e., 2-4µm thick epi on ~0.7mm CZ substrates) are used for bipolar ICs, including ASICs and microprocessors. As the industry evolves toward 256Gbit DRAMs and bipolar ICs with 180-million transistors, epi wafers as well as silicon-on-insulator (SOI) wafers (i.e., 50-200nm thick silicon, <200nm SiO2 on ~0.7mm thick CZ substrates) will be used increasingly along with polished CZ wafers (see "Polished silicon alternatives," page 71).
The semiconductor industry has seen quality improvements in silicon crystals grown by the CZ technique continually over the years. In today's emerging sub-0.25µm IC manufacturing, 200mm wafers meet ever-tightening wafer quality requirements in terms of the crystalline defects, heavy metallic impurities, oxygen level, oxygen radial uniformity, minority carrier lifetimes (recombination and generation), particles, etc. [1]. While production of 300mm wafers is just beginning, the required quality as updated in the 1999 International Technology Roadmap for Semiconductors (see table on next page) will be met by further developing and refining crystal growth technology being applied and developed for 200mm wafers, particularly as it is applied to point and secondary defect control and control of oxygen.
Point and secondary defect
On the Roadmap, surface pits or crystal originated particles (COPs), often called localized light scatterers (LLS), become increasingly problematic. COPs are the agglomeration of point defect vacancies (i.e., vacancies and silicon self-interstitials in silicon) during CZ growth. They can be mapped with a particle counter.
Point defects are incorporated in silicon when it crystallizes. Computer simulation estimates their thermodynamic equilibrium concentrations at ~1x1015/cm3 for vacancies and about 20% less for the interstitials at the melting point (mp) of 1412°C [2, 3]. As the crystal cools continually during CZ crystal growth, the solubility of the point defects decreases, resulting in supersaturation. Intense recombination of vacancies and interstitials takes place at a high temperature range (mp to ~1200°C). Also, some out-diffusion of interstitials occurs near the periphery of the crystal surface.
Computer simulation shows ~10% of the original point defects in both vacancy and interstitial rich regions survive after the intense recombination regime [2, 3, 4], but they are still in a high degree of supersaturation below about 1200°C and form agglomerates or clusters. Survival of minority point defects in the vacancy and interstitial rich regions is about 1%. Vacancies agglomerate into octahedral voids at about 1150-1080°C [5].
Problematic COPs are due to such voids intersecting the wafer surface or present in the immediate subsurface (Fig. 1). Octahedral voids are bounded by the lowest energy {111} planes.
Supersaturated interstitials are known to form large dislocation loops of a low density if supersaturation is sufficiently high. However, technology for today's 200mm wafers tailors crystal growth conditions to alleviate formation of the dislocation loops.
Formation of secondary defects originating from point defects are controlled today both by proper engineering of the hot zone design, which provides optimal thermal environments, and by selecting proper crystal growth conditions.
Typical silicon wafers being used today have an interior vacancy-rich region surrounded by an interstitial-rich edge. These regions are separated by the vacancy-interstitial (V/I) boundary that occurs at a critical value of a parameter defined [6] as
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where v is the crystal growth rate in mm/min and G(r) the axial temperature gradient in °K/mm at the crystal-melt interface and radial position r.
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G at the crystal center is usually lower than at the crystal surface. In addition, v is the same across the crystal growth interface at a given pull rate. Thus, the value of v/G is highest at the radial center and decreases continually toward the crystal edge in conventional CZ silicon crystal growth. The wafer center region inside the V/I boundary is vacancy rich characterized by v/G( r) >xic, while the edge region outside the V/I boundary is interstitial rich with v/G(r) <xic.
The concentrations of the vacancies (CV) and the interstitials (CI) at a given radial position r relative to those of the equilibrium levels of CVeq and CIeq at about 1200°C after passing the transient recombination and out-diffusion regime between mp and ~1200°C are apparently, as proposed here, exponentially proportional to the difference of v/G(r) from xic, i.e.,
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where a and b are not known at this time. Radially, high supersaturation of vacancies and thus more voids are formed at the crystal center region. On the other hand, high supersaturation of interstitials is present at the crystal peripheral region. But because of out-diffusion of the interstitials to the crystal surface, high supersaturation of interstitials occurs at some distance from the edge. (The interstitials diffuse about 10 times faster than the vacancies near the mp of silicon.)
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Figure 1. COP images measured on polished wafers by atomic force microscopy: a) single COP, b) dual COPs, c) cross section of part a, d) schematic of part c.
In the v/G ratio, thermal gradient (G) is controlled by the thermal environment with a proper hot zone design in the crystal growth system and by melt convection. The growth rate (v) is controlled by the crystal growth process. Computer simulation both of the melt convection and especially the thermal distribution in the growing crystal provides a valuable design tool for optimizing v/G.
"Virtually perfect silicon"
Important for future silicon growth technology, efforts are being made in the silicon crystal growth industry to establish a condition of
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along the whole radius at the crystal-melt interface. This condition [7] will provide silicon crystals and wafers with point defects of quasi-equilibrium concentrations so the point defects are not super-saturated and COPs are not formed in the vacancy rich region; likewise no large dislocation loops are formed in the interstitial rich region.
Such point-defect equilibrated silicon crystals give rise to proposed "virtually perfect silicon" (VPS) because the V/I boundary and ring-OSFs (oxidation induced stacking faults) are not present; a VPS wafer appears to the device as "perfect or pure." Importantly, the COP level in a VPS silicon wafer will be negligible so yield and performance of ULSI devices with polished VPS wafers will be enhanced to a level of epi wafers.
Today, VPS silicon is being developed for 200mm and subsequently for 300mm wafers. Development concerns include the significant difficulty of optimizing the hot zone to achieve v/G(r) approximately equal to xic along the whole length of the crystal and the needed relatively slow pull rate, which respectively are not beneficial in terms of the yield and throughput of the crystal manufacturing.
Fast-pulled silicon
Another approach being pursued to achieve a wafer quality similar to VPS material is crystal growth at a pull rate approximately three to four times faster than the conventional rate, combined with post growth high temperature anneal of polished wafers —"fast-pulled silicon" (FPS).
With FPS, although G has to be increased to some extent to enable the high pull rate, v/G increases substantially so that v/G becomes much larger than the critical value xic = 0.138 mm2/min-°K; the crystal becomes completely vacancy rich, and the vacancy concentration below about 1200°C after passing the recombination regime becomes much larger than the equilibrium level, i.e.,
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Due to the high pull rate of FPS, the crystal passes fast through the 1150-1080°C COP forming range so only COPs of smaller sizes and high density can be formed. Furthermore, such small size voids near the wafer surface can be easily removed by post-growth wafer annealing. Doping with nitrogen contributes to minimize void formation in FPS [8].
FPS development concerns include the effect of relatively high vacancy concentrations remaining in the wafer, which could cause anomalous oxygen precipitation that degrades device performance and yield, for instance in terms of DRAM refresh time [9]. The necessity of proper denuded zone formation in the wafer through high temperature annealing steps is also a concern. On the other hand, the advantages of FPS crystal growth include the possibility of high throughput, high yield, and potentially lower cost.
Controlling oxygen with cusp MCZ
Oxygen in silicon interacts with the point defect agglomeration. Octahedral voids are deposited at the inner wall of the voids by oxygen precipitates formed due to supersaturated oxygen segregating from the silicon matrix [10]. Vacancies enhance the oxygen precipitation behavior. For example, residual vacancies at the edge annulus of a vacancy-rich wafer center region — where voids are formed consuming supersaturated vacancies — enhance oxygen precipitation, forming nuclei for the stacking faults in the ring-OSF region. This can cause stacking faults to form during some high temperature device processing steps, as well as in regular OSF testing.
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Figure 2. Cusp magnetic CZ silicon growth uses two opposite vertical magnetic fields.
Today's 200mm wafers have an oxygen level of 19-31 ppma (ASTM 1979). Oxygen in CZ silicon crystal comes from dissolution of the quartz crucible; it is transported to the crystal-melt growth interface and segregated into the crystal. Transfer of oxygen in the melt is affected substantially by the melt convection. As crucible diameters increase, melt convection becomes increasingly more of a turbulent fluid flow.
Melt convection is suppressed most effectively by applying a magnetic field —magnetic Czochralski (MCZ) [11]. For 200mm crystal growth, MCZ with a cusp-type magnetic field [12] (Fig. 2) has been developed successfully; it controls oxygen concentration to 19-31 ±2 ppma (or less) with a radial gradient of 5% or less.
For 300mm silicon crystals, and subsequently 450mm, cusp MCZ will be effectively used not only to control oxygen, but more importantly, to enable single crystalline growth itself. Melt temperature fluctuates severely due to turbulent melt convection in a large size melt for 300mm crystal growth; this does not provide stable crystal growth conditions with conventional CZ systems (non-MCZ).
A further benefit of MCZ is to minimize emission of SiO2 particles from the crucible wall in contact with the silicon melt, which is detrimental in causing loss of the single crystalline growth when the particle hits the crystal growth interface.
An oxygen level of 18-31 ±2.0 (or less) ppma with a radial gradient less than 5% needed in 2000-2005 can be achieved effectively for 300mm wafers by cusp MCZ by applying proper magnetic field strength in conjunction with adjusting crystal growth conditions.
Conclusion
Two CZ silicon crystal growth processes, VPS and FPS, are being developed to control the point and secondary defects in silicon, and to alleviate COP issues for ULSI devices. Voids are not formed in the VPS, but yield and throughput are of concern due to severe difficulty of establishing hot-zone and growth conditions and relatively low pull rate. With FPS, small voids are formed and, combined with post-growth wafer anneal, form a void-free denuded zone; nitrogen doping is quite beneficial for FPS. Pull speed is about 3-4 times the conventional, possibly lowering wafer production cost. Cusp MCZ is expected to achieve required oxygen levels and good radial uniformity for 300mm and 450mm crystal growth.
Acknowledgments
Part of this article is based on an invited talk at the 6th Korean Conference on Semiconductors (KCS'99), February 1999, in Seoul, Korea. The author thanks Bo-Yong Lee of LG Siltron for providing AFMs.
Kyong-Min "George" Kim received his BS in chemical engineering from Seoul National University and his Diplom-Chemiker and PhD in physical chemistry from Braunschweig Technical University in Germany. After post-doc research in the electronic materials group at MIT, he held R&D positions at IBM and MEMC, both involving developing advanced CZ/MCZ crystal growth technology. Kim is the technical consultant and president of KMK Associates. He has been awarded 23 US patents, and has written 44 technical papers. Kim has received 4 Plateaus of Invention achievement awards from IBM, and the Sky Lab achievement award from NASA. KMK Associates, 1199 Whitmoor Dr., St. Charles, MO 63304; ph 636/447-3278, fax 636/922-0564, e-mail [email protected].
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