Issue



European technologists to combine Cu/low-k and packaging


12/01/2001







Belgium's independent R&D center IMEC, located in Leuven, has begun research to develop technology that will give the industry integrated wafer level packaging on copper low-k IC interconnect, to be performed in wafer processing's back end of the line (BEOL). IMEC technologists view such novel technologies as fundamental for leading-edge CMOS technologies, including IMEC's work to benchmark and leverage CMOS and Bi-CMOS for RF applications. This work will enable products operating well into the 5-25GHz microwave radio frequencies.


Wafer level flip-chip redistribution achieved with one additional metal interconnect layer and a three- or four-mask process including bumping by solder stencil printing or electroplating. Shown are a 3 x 3mm die with 250mm pitch, providing 84 I/Os of electroplated bumps, and a close-up of the bumps (top right).
Click here to enlarge image

Brief details on the new program were given by Karen Maex, IMEC's strategic research coordinator for interconnect technologies and silicides, at the center's annual research review meeting held recently in Leuven, Belgium (see "Some current R&D efforts at IMEC" below). Maex said, "We have designed this program to help establish the future functionality of the package as a provider of global interconnects with the chip."

To address the weakness and corrosion susceptibilities of low-k dielectrics, the program first will determine an improved chip passivation to cover Cu low-k interconnect structures. Maex said, "With copper interconnect pads, there are also issues with oxidation, wire conductability, and interconnect reliability. So we are also looking at optimizing bond pad design and direct copper wire bonding onto copper bond pads. For the latter, several tests have already proven feasibility, but more work is needed before this technology reaches the productivity of current state-of-the-art, fine-pitch gold wire bond equipment."

The new IMEC program has also targeted solutions to I/O density problems using an I/O bond pad redistribution layer added, at the wafer level, on top of copper low-k integration (see photomicrograph). "Using one additional metal layer, we will redistribute perimeter contact pads into an area array," Maex said. "Then, on these contact pads, we will study solder bumping for flip chip connections. Here, given environmental requirements to eliminate lead from electronics, we will be focusing on small pitch lead-free bumping. One very significant advantage of this redistribution technique is that the additional metal layer can be used for high-speed interconnect lines across a die, clock redistribution lines, and even to realize high-Q inductors on chip."

Because interconnect delay will seriously limit performance as the industry scales to smaller nodes, one of the long-term strategies of the new IMEC program is to develop solutions for minimizing overall on- and off-chip signal delay. Maex commented, "Introduction of copper and low-k has only incrementally improved the propagation velocity situation with ICs. We see that the integration of packaging with BEOL processes will allow for new interconnecton concepts that can solve signal-delay problems."

Some current R&D efforts at IMEC
From the broad array of topics addressed, other significant new technologies and milestones announced at IMEC's Annual Research Review Meeting 2001 included:

  • The start of a three-year program to develop, benchmark and leverage 100nm CMOS and BiCMOS for 5-25GHz RF applications, the work to include front-end device optimization and advanced integration of BEOL and post-processed passive devices;
  • Imminent installation of a 157nm mini-scanner from ASML to continue the center's development of advanced optical lithography (IMEC has been developing 193nm lithography for three years, has just installed a high-NA ASML 5500/1100, and reports that suitable 193nm resists are available from "nearly all major resist suppliers. These are single-layer resists generally selected for a specific layer and used with ARCs."); and
  • Progress with research programs looking at new device architectures compatible with silicon-based technology (i.e., 45-22nm gate length field effect transistors) and future alternatives such as multiple gates (i.e., vertical devices with and without bandgap engineering or "FINFET" structures), FDSOI (i.e., ultrathin fully depleted SOI CMOS with conventional gate stacks), and high-mobility strained Si/SiGe CMOS for sub-32nm gate lengths.