rf and microwave plasma for resist and post-etch polymer removal
12/01/2001
COVER FEATURE
Wes Graff, Mark Matson, Novellus Systems Inc., San Jose, California
Tom Kellner, Tammy Pluym, Steve O. Nelson, Philips Semiconductors, Albuquerque, New Mexico
overview
An effective method for removing photoresist and post-etch polymers at the transistor gate level, while removing less oxide than more traditional HF wet cleans, has been developed. This low-temperature clean process, which utilizes an O2, CF4, and H2O (gas) chemistry with both radio frequency and downstream microwave plasma excitation, is shown to have no impact on gate oxide integrity and capacitance-voltage performance.
The semiconductor industry has traditionally used high-temperature microwave (MW) ashing processes for photoresist removal. A recurrent problem with these oxygen-based MW plasmas is inadequate removal of certain polymers because of their low volatility and insoluble nature. A polysilicon gate etch is typically followed by cleaning with a standard high-temperature (270°C) O2/N2 MW plasma process, then by HF and Piranha cleaning (sulfuric acid and H2O2). Web-like polymer residues are commonly left behind.
The difficulty in removing residues has increased with the conversion to more selective polysilicon etch chemistries. With the demanding requirements for profile control, reactive ion etching (RIE) of polysilicon often utilizes O2 or He/O2 gas additives to the typical HBr and Cl2 chemistries, which help oxidize the poly sidewalls to prevent lateral etching. This O2 addition has the adverse effect of converting the SiBrx and SiClx residues to less volatile compounds such as SiOxBry and SiOxCly [1]. Additional integration trends have also increased the complexity of resist stripping and polymer removal. For example, the conversion to deep ultraviolet (DUV) resists and antireflective (AR) coatings makes resist removal and cleaning more challenging. DUV resist tends to form a polymeric surface layer during an RIE etch that can be difficult to remove and will often redeposit on the wafer surface after a traditional MW ash process. AR coatings pose a problem because they are often removed at a much slower rate than photoresist.
Since traditional MW ashing processes and Piranha/HF wet cleans can be ineffective in removing residues, a more advanced process is required. For this reason, a process has been developed on the Novellus PEP Iridia DL [2], which is capable of generating both rf and MW plasmas with a variety of process gases. The concurrent use of rf and MW was found to be a key component for removing polymers at the gate polysilicon layer (Fig. 1). The addition of H2O to the more traditional O2/CF4 chemistry allows for a slower gate oxide removal rate.
Process development considerations
With traditional MW ashing processes, high temperatures and high oxygen concentrations are the main process parameters used to increase resist removal rates. This poses a problem for silicon-containing residual polymers because the polymers readily oxidize at high temperatures and once oxidized, become increasingly difficult to remove. One solution is to use CF4 or other fluorine-containing gases to volatilize the polymers. But it has been shown by Rotondaro et al. [3] that the SiO2 etch rate can exceed 30Å/min at 250°C, resulting in excessive oxide loss. Since the oxidization of post-etching residues and the accompanying oxide loss are unacceptable, high-temperature processing is not a viable solution for residue removal. With the established need for low-temperature processing to maintain oxide selectivity comes the challenge to provide a sufficiently high resist removal rate.
The use of fluorine-containing gases in a resist removal process has many advantages. In the form of CF4, the addition of small amounts of fluorine is known to increase the concentration of atomic oxygen and therefore increase the resist removal rate [4]. Note the standard reaction for resist removal:
CxHy + O → COz + H2 + H2O
Fluorine also reduces the activation energy required for the resist removal reaction, further increasing the removal rate [4], so that a manufacturable resist strip process at lower temperatures is possible.
Another benefit of fluorine is that it volatilizes the post-poly-etch residues (SiOxBry and SiOxCly) and converts the polymers into a more water-soluble residue that can be removed in a subsequent DI water or Piranha rinse. Solis et al. [5] previously observed the effectiveness of CF4 in removing post-etch residues. However, the negative effect of CF4 is the removal of exposed oxide, nitride, and silicon layers.
Low-temperature O2/CF4 MW plasma processes have been thoroughly studied to prove their effectiveness in post-etch residue removal rates [4-8]. The challenge is to strike a balance between removing polymers, removing resist at a sufficient rate to maintain reasonable tool throughput, and minimizing oxide loss. Based on the work of Hayasaka et al. [7], it has been shown that H2O is a good source of hydrogen atoms required for the combination reaction with fluorine to produce vapor HF, via the following reaction scheme:
H2O + 2F → O+ 2HF (2)
This reaction is important because the reduction of atomic fluorine in the plasma reduces oxide loss, while the HF aids in polymer removal.
Residues can also be removed by using a traditional HF wet clean, but such a process has been shown at Philips to remove up to 60Å of oxide/min. This is an unacceptable amount of oxide loss. The thin layer of oxide beneath the gate is exposed to the plasma and etchants during clean processes. Etch processes using either traditional HF or MW ash utilizing O2 and CF4 can undercut the gate oxide and degrade transistor performance. This concern is even greater for very thin gate oxides, used in more advanced microprocessors. Thinner gate oxides will require improved selectivity to SiO2 to ensure gate oxide integrity (GOI) for reliable transistor performance [9].
The combination of achieving higher polymer removal rates with increased selectivity to gate oxide highlights the need for advanced dry-clean processes in the future. The goal of this effort was therefore to develop a CF4-based clean recipe that efficiently removes the photoresist, ARC, and residues, while minimizing oxide loss and maintaining GOI.
Experiment
The poly clean process was developed on the Iridia DL. The chamber features a 1.8kW downstream MW (2.45GHz) plasma source and an rf-biased platen (13.56MHz, 500W generator), which can be run independently or simultaneously. To minimize oxide loss, this specific process is run at a low temperature, below 100°C, controlled by the platen heat exchanger.
Experiments with CF4 and H2O flows showed the ratio of CF4:H2O was critical to maintain good selectivity to thermal oxide. Process optimization by design of experiments (DOE) techniques targeted acceptably high resist removal rates and minimal oxide etch rates. The final process utilized a single-step O2 MW + rf plasma with 3% CF4 and a CF4:H2O ratio of 0.67.
Optical emission spectroscopy (OES) was used to study mechanisms for achieving high etch selectivity to oxide. Spectra were obtained on the Verity SD1024 Spectrograph, coupled to the Iridia endpoint window via a fiber optic cable. The spectra were collected at a frequency of 2/sec and averaged over the entire process time.
New plasma processes typically generate concern about GOI and transistor reliability. A series of capacitance-voltage (CV), field to breakdown (Ebd), and charge to breakdown (Qbd) tests were performed to determine if the quality of the gate oxide was maintained.
Capacitance-voltage measurements were performed using thermally oxidized (500Å layers) test wafers subjected to sputtering and alloying. The CV test was performed on a Materials Development Corp. (MDC) DuoCHUCK Model 8512 and an MDC CSM/16 semiconductor measurement system, incorporating a Boonton 72B capacitance meter and a Keithley 595 quasistatic CV meter. Three probes/wafer were used and run through a -5 to +5V sweep at room temperature and again at 250°C. Flat band voltage shifts must fall within a -0.300 to +0.050V range to meet Philips' internal test specifications.
GOI tests were performed using test wafers with 50Å gate oxide. One wafer was run in each chamber of the Iridia using the CF4 poly clean process, while eight control wafers were cleaned on a standard O2/N2 MW plasma process on another Iridia platform of identical configuration. The wafers were then probed on a Keithley S400 parametric test system and a horizon test system with a Wentworth Labs probe card. The maximum Ebd was tested on 55 sites/wafer. The voltage was ramped from 0 to 100V at a rate of 2x109V/m multiplied by the oxide thickness. The breakdown or triggering current (Ibd limit) was based on an internal specification of 200A/m2 multiplied by the area of the device. The Qbd was tested on five sites/wafer. Test and control wafers were subjected to multiple iterations in a graduated test current until the voltage across the gate oxide fell to a critical value, indicating breakdown.
Results and discussion
The photoresist etch rate and oxide loss rate were both directly proportional to the CF4:H2O ratio and to rf power. Under the experimental conditions in Fig. 2a and b, resist etch rates varied from 647 to 6077Å/min and oxide etch rates from -1 to 91Å/min. By selecting a CF4:H2O ratio <1, it was possible to achieve >2500Å/min blanket resist removal rates and <2Å/min oxide loss. Oxide loss measurements from product wafers have consistently shown less than 6Å loss on the optimized CF4 poly clean process.
The importance of the H2O to the process recipe was emphasized when H2O was eliminated — oxide loss increased to 190Å. The optical emission spectrum (Fig. 3) verified that the addition of water vapor results in a reduction of free fluorine and hence the creation of HF species per the mechanism proposed by Hayasaka et al. [7] and shown in Reaction 2. The emission spectra also illustrated the other benefit associated with the addition of H2O, an increase in atomic oxygen. Fujimura et al. [4] also observed that the addition of water would result in an increase in atomic oxygen in O2 MW plasma.
Through the combined addition of CF4 and H2O to the low-temperature O2 plasma, we have: 1) increased the atomic oxygen concentration, which increases the removal rate of resist; 2) controlled the concentration of atomic fluorine, therefore reducing oxide loss; and 3) increased the removal rate of resist by lowering the activation energy required to initiate the resist-ashing reaction.
These factors combine to create a high-throughput clean recipe with high selectivity to gate oxide.
Additional resist removal measurements indicate synergistic effects of rf and MW in the same process step. In the presence of both MW and rf, resist removal is additive. This is a key aspect to maintaining acceptable resist strip rates while minimizing oxide loss. Although resist removal was considerably higher with the omission of water, the absence of water causes unacceptably high oxide loss.
The effectiveness of the CF4 poly clean is shown in Fig. 4, indicating the complete removal of residue. Wafers cleaned using the CF4 poly clean process (Fig. 4b) were compared to the standard MW recipe (Fig. 4a) and to CF4 poly clean applying only MW power (Fig. 4c) and only rf power (Fig. 4d). The standard MW recipe left web-like residue, whereas no residue remained on the wafer run on the CF4 poly clean recipe. The same recipe failed to remove all the residues when either rf or MW power was omitted.
A comparison of CV measurements on wafers cleaned with the CF4 poly clean recipe to a standard MW process (270°C, O2, MW downstream processing) showed comparable results, neither having a significant flat band voltage shift. The CV wafer run with the CF4 poly clean process had a flat band voltage shift of 0.027V after a positive voltage was applied during the 250°C temperature stress and a shift of -0.02V with a negative voltage. Similarly, the standard MW process had a -0.025 voltage shift with a positive voltage, and a 0.011V shift with a negative voltage. Both wafers were within reference values of -0.3 to 0.05V, suggesting no mobile ion contamination.
As shown on the probability plots in Figure 5a, no charging damage with the CF4 poly clean recipe was detected. The plots show the GOI data (4750:1 antenna ratio) for a standard MW process and the CF4 poly clean process. In the field to breakdown plot, there were no failures below 2x109V/m. Since this number is over an order of magnitude higher than the specification limit of 8.3x108V/m, there is no charging concern for the CF4 poly clean. From the Qbd tests (Fig 5b), there were no sites for the CF4 poly clean that failed below the 1C/cm2 specification limit. Based on the comparison of these trends, both processes are comparable with respect to GOI.
Conclusion
After completing the development process, the CF4 poly clean recipe was implemented in production at Philips on the 0.25µm technology node and is expected to be extendable to the 0.1µm level. While other sources have proposed the use of an O2, CF4, H2O plasma utilizing MW downstream plasmas, the present work shows the significant benefits achieved with the addition of rf power. This combination is critical for removal of polymers and increasing the resist removal rate with no significant difference in antenna structure GOI (Ebd and Qbd) or CV measurements when compared to standard high-temperature O2/N2 MW processes. These results alleviated concerns about device reliability present when any new plasma processes are implemented in the process flow. Additional efforts are currently in progress for contact, via, and post-metal cleans. These integrated ash and clean processes will simplify the process flow and significantly reduce the needs for HF or solvent processing.
Acknowledgments
We would like to express our sincere gratitude to Aditya Deshpande for his assistance in CV interpretation; Randy Nguyen and Deanna Rieden for their help in GOI processing and assistance with interpretation; and Jerry Winniczek of Novellus for his assistance with optical emission spectroscopy and data analysis.
References
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- Private communications.
Wes Graff received his BS in chemical engineering from Texas A&M University. He is a senior process engineer in the Surface Integrity Process Development Group at Novellus Systems, responsible for integration activities related to dry-clean and etch applications. Novellus Systems Inc., 4000 N. First St., San Jose, CA 95134; ph 512/314-3765, e-mail [email protected].
Mark Matson received his BS in mechanical engineering from the University of New Mexico. He is a process engineer at Novellus Systems.
Thomas Kellner is pursuing his BSEE at the University of New Mexico. He has worked for the Advanced Technology Development Department at Philips Semiconductors for two years.
Tammy Pluym received her BS in chemical engineering from Rice University and her MS in chemical engineering from the University of New Mexico. She was a process development engineer for Philips and is currently at Emcore Corp.
Steve O. Nelson received his PhD in materials science and engineering from Iowa State University. He is a senior development engineer at Philips.