Issue



Modeling causes and effects of semiconductor backend cycle time


12/01/2001







Appa Iyer Sivakumar, Nanyang Technological University, Singapore
Ngai Fong Choong, Chin Soon Chong, Gintic Institute of Manufacturing Technology, Singapore

overview
Modeling work has investigated controllable parameters — such as lot release, heuristic scheduling, machine uptime, etc. — that determine cycle time and throughput in a complex semiconductor manufacturing backend. While no single parameter control gave best performance, the most significant was lot release scheduling to the first operation. Smooth lot release scheduling of demanded capacity gave shorter queue times and a narrower cycle-time distribution.

Using a simulation model, we analyzed a semiconductor manufacturing backend operation to determine the effects of controllable variables on the typically observed wide variation in production cycle times and throughputs. In this work, we defined lot cycle time as the duration from the first operation to packaged ICs ready for shipment.

Our analysis used live data from a major semiconductor facility in Singapore, which is currently manufacturing more than 275 million ICs/year. In most backend operations, there are many products in process (i.e., up to 2000), each requiring a different processing sequence; many process flows go on at one time.


Figure 1. Altered input variables and model output variables on which effects were analyzed.
Click here to enlarge image

The longest cycle time of 98% of the lots completed/month is a commonly used measure of cycle-time spread in semiconductor manufacturing. Cycle time for assembly operations is typically 3-6 days and test operations 1.5-15 days. We wanted to identify factors that influence these variations so they could be controllably reduced.

The modeling
Our simulator was Brooks Automation AutoMod. It uses features such as machine definition; product process-step routes; yield; rework; machine units/hr; batch process time of ovens, etc.; mean time between failures (MTBF); mean time to repair (MTTR); setup time matrix; and preventive maintenance (PM) schedules. Specifically, we modeled 512 individual production machines in 184 station families, and 1274 IC products, each with a unique process sequence. This involved defining process time, yield, and distribution arguments. We also modeled internal transport and material-handling times with appropriate distribution arguments.

In our test factory, the general lot-sequencing rule is "earliest start date" (ESD). We specified our model with the ESD dispatch rule for all operations except lot starts; these were modeled based on a deterministic schedule used in the actual factory.

We defined machine unavailable times (e.g., shift breaks, downtime, and PM) in a calendar file. Shift, meal, and tea breaks were simulated for all machines except those capable of batch processing. We modeled downtime with MTBF and MTTR distributions, and PM using actual plans, with distributions on the duration of PM time.

When modeling, we noted that work in progress (WIP) reached realistic steady levels over 10 days of simulation after a zero inventory start. So, we simulated a 14-day warm-up period before capturing our modeling data during 28 subsequent days.

Because of various complexities, we did not model testers, burn-in, test binning, or operators, instead substituting assumptions that could have some effect on model validation.

Verification, validation
We verified our model (i.e., Did we build the model correctly?) with iterations from simple output checks to complex walkthroughs using flow charts, and finally using a published "trace" technique [1].

We validated our model (i.e., Did we build the correct model?) using a "correlated inspection approach" [1]. This involved collecting historical data from the factory and comparing model and system outputs of selected variables after the warm-up period. We used input data for multiple replications with different random seed numbers. With each replication, we analyzed a set of output variables to construct 90% confidence intervals [2].

Using this technique, we validated throughput, cycle time, and WIP levels for IC groups of 1) products that are only assembled; 2) products that only undergo test processing; and 3) products that are both assembled and tested. Each group differs significantly in terms of the combination of process equipment, process routes, and factory resources used for completion. We found that modeled mean throughput for the third group was ~7.3% higher than factory throughput, and the modeled output of 98th percentile cycle time was ~11% higher than the factory. We considered these acceptable enough validations of our model to fulfill our objectives.

The conclusions below are for just the third group — completely assembled and tested ICs.

Modeling results
We used our validated model as a base and quantified the effects of the varied inputs against the base, not against the factory, so we could detail the relative merits of the input variables (Fig. 1).


Figure 2. Lot size relationship of cost and time.
Click here to enlarge image

Theoretical cycle time is a critical factor affecting actual cycle time. We define it as the sum of pure process time of a given IC based on a fixed lot size, excluding material transport, handling, and queuing times. Our modeling involved 1500 ICs for each specific IC product. Because so many parts go through an assembly operation, we typically see wide variations in theoretical process times caused by different lead counts, different test times and test steps, different package molding requirements, etc. In fact, such variability has been identified as one of the major causes of congestion in semiconductor assembly [3] and therefore contributes to variations in cycle time and WIP levels.

Theoretical ratio or flow factor is often used to benchmark competitiveness of operations [3]. Often a theoretical ratio based on mean theoretical process time is used (e.g., 98th percentile cycle time/mean theoretical cycle time = theoretical ratio of 98th percentile cycle time). While we used this benchmark convention, it is important to realize that due to wide variations in theoretical process times in assembly operations, theoretical ratios based on mean values may be misleading.

Our modeling showed:

  • The queuing time component of 98th percentile cycle time is an overwhelming value of between 3 and 5 times that of all other no-value-added times and a major contributor of cycle-time variation.
  • The improvements gained in material handling, setup, PM, and machine failures were marginal, being <3% of the 98th percentile cycle time and below the validation gap (i.e., the statistical difference between a simulation model and the factory).
  • Keeping lot-start volumes constant, the effect of reducing lot size (i.e., in one of our tests we halved lot size) on cycle time and throughput was not significant. In addition, setting a lot size ceiling seems to deteriorate mean cycle time with some impact on cycle-time spread. (Thorough lot size analysis requires extended study because lot size distribution is a complex variable affecting both cycle-time distribution and throughput [4].)

    We examined the gross effect of lot size on relative cost and average cycle time on a medium volume product in factory (Fig. 2). The cost values were based on relative costs identified by the factory. As lot size was increased, setup time (and setup cost) was reduced at the expense of cycle time translated as stock carrying cost. It can be seen that from an overall point of view, a good operating region for the lot size is between 1500 and 2300 ICs.
  • All three heuristic machine-scheduling rules [5] — first out (FIFO), least pieces ahead (LPA or LWNQ [6]), and same setup (SSU) — gave an improvement in mean cycle time at the expense of cycle-time spread indicated by the 98th percentile cycle time. SSU enables improvement in both mean cycle time and throughput at the expense of ~12% increase in cycle-time spread. FIFO and LWNQ showed a mean time difference of 3.4%.
  • Increasing start volume (our range was -5% to +15% of original lot quantity) while maintaining original lot release times does not result in an increased throughput, but deteriorates both 98th percentile and mean cycle times. On the other hand, significant improvements of 35% and 30% were achieved in mean and 98th percentile cycle times with a marginal improvement in throughput when lot sizes were selectively reduced.

    For example, a 10% reduction of start volumes across all products reduces cycle-time variation by 10% with a 2.5% loss in throughput. However, when the same volume reduction is selectively realized on lots routed through constraint machines (i.e., machines whose available capacity is less than or equal to the demand on them or whose utilization is highest), the cycle-time distribution is reduced by 30.4% with a 1% improvement in throughput.
  • Using a uniform lot-release start schedule — reassigning new release times and dates based on available daily capacity in terms of processing hour requirements on machines — gave a 63% reduction in 98th percentile cycle time. Mean cycle time also showed a significant reduction and maximum cycle time was halved. In these tests, despite a 19% reduction in start volumes, throughput was only reduced by 3.5%, indicating a significant reduction in WIP level. Analysis showed that almost the entire reduction is due to queuing time.

This confirmed that an erratic schedule is one of the main causes of excessive cycle-time distribution, long no-value-added queue time, and failure to achieve potential throughput. In addition, loading lot starts closer to capacity gives the best performance in 98th percentile at the expense of throughput. Loading above available capacity has the attraction of minor increases in throughput and machine utilization at the expense of cycle-time spread. Loading to capacity results in probably the lowest 98th percentile, but total potential throughput capacity may not be realized. This is mainly because no static capacity calculation can predict exact available hours of every machine family.

A leveled loading pattern with slight overload above capacity would enable lots to use "opportunity time slots" (i.e., time slots of a machine in a typical production schedule that arise as result of a stochastic event, such as a breakdown of an upstream machine) arising from the shop floor dynamics. This is a potential area of further research.

Conclusion
Using a simulation-based cause and effect analysis of cycle-time distribution in a semiconductor-manufacturing backend operation, we have shown that theoretical cycle time is an important variable that affects cycle-time variation. The influence on cycle-time spread of factors such as internal material handling, PM, machine failure, and setup is relatively small. Heuristic scheduling policies have some effect on cycle-time spread and no single policy on its own gives the best performance. In general, however, ESD heuristics showed the narrowest cycle-time distribution.

The most significant conclusion from our analysis is that lot release scheduling to the first operation has the greatest impact on cycle-time variation and throughput in a semiconductor-manufacturing backend. Smooth lot-release scheduling in terms of demanded capacity gives short queue time and a cycle-time distribution that is significantly narrower than that of erratic lot-release scheduling. Lot-release scheduling above capacity constraint does not improve throughput, but adds substantially to cycle-time spread.

Acknowledgments
AutoMod is a trademark of Brooks Automation Inc.

References

  1. A.M. Law, W.D. Kelton, Simulation Modeling and Analysis, McGraw-Hill Inc., New York, pp. 298-323, 1999.
  2. A.I. Sivakumar, "A Simulation Based Analysis of the Effect of Scheduling and Lot Release on Cycle Time Distribution and Throughput in Semiconductor Backend," Proc. of Intl. Conf. Modeling, Analysis of Semi. Mfg., pp. 206-211, 2000.
  3. W.J. Hopp, M.L Spearman, Factory Physics: Foundations of Manufacturing Systems, Times Mirror, US, 2000.
  4. J. Potoradi et al., "Determining Optimal Lot-size for a Semiconductor Backend Factory," Proc. of 1999 Winter Simulation Conf., IEEE, pp. 720-726.
  5. S.C.H. Lu et al., "Efficient Scheduling Policies to Reduce Mean and Variance of Cycle Time in Semiconductor Manufacturing Plants," IEEE Transactions on Semiconductor Manufacturing, Vol. 7, pp. 374-388, 1994.
  6. L.M. Wein, "Scheduling Semiconductor Wafer Fabrication," IEEE Transactions on Semiconductor Manufacturing, Vol. 1, No. 3, August 1988.

Appa Iyer Sivakumar received his bachelors in engineering and his PhD in manufacturing systems engineering from the Univ. of Bradford. He is associate professor at the School of Mechanical /Production Engineering, Nanyang Technological Univ., 50 Nanyang Ave., Singapore 639798; ph 65-790-5050, fax 65-792-4062, [email protected].

Ngai Fong Choong received her bachelors and masters in engineering from the National Univ., Singapore, and is a research fellow at Gintic Institute of Manufacturing Technology.

Chin Soon Chong received his degree in electrical/electronics engineering from City Univ., London, and his masters of engineering from Nanyang Technological Univ. He is a research fellow at Gintic Institute of Manufacturing Technology.