A new generation of IC processing: Low-power, high-performance SOI CMOS
11/01/2001
MATERIALS (SOI)
Jean-Luc Pelloie, Silicon-on-Insulator Systems and Integrated Circuits (SOISIC), Grenoble, France
André Auberton-Hervé, Silicon-on-Insulator Technologies (SOITEC), Bernin, France
overview
To take full advantage of the SOI structure, device architecture and design issues must be addressed. While circuit design is achieved with standard CAD tools, specific modeling is required to take into account the physical design of the devices and unusual electrical characteristics.
Industry support is growing for SOI substrates as the successor to silicon epitaxy for current CMOS scaling and ultimately for high-performance logic circuits at 100nm. The goal relies on a secure supply of SOI wafers, with the next step, 300mm wafers, expected to be available in volume quantities by 2003. To enable chipmakers to take full advantage of the SOI structure, device architecture and design issues must be addressed.
Device architecture choices for SOI CMOS
SOI technologies offer solutions to low-power, high-performance applications. The key device-architecture issue is the choice between partially depleted and fully depleted devices (referring to the channel region of the transistors). While each structure has pros and cons, the choice needs to be balanced between process complexity and performance. Each has a specific impact on SOI material requirements.
For the 0.25µm generation and below, the underlying silicon substrate plays only a mechanical role and is generally electrically grounded. The presence of a buried oxide completely separates an SOI device from its neighbors, typically by shallow trench isolation (STI). The trench is formed by etching into the SOI layer; the depth is fixed by the silicon film thickness — generally <0.2µm. The underlying insulator layer (also called the buried oxide) provides an etch stop during formation of the trench. Subsequent planarization (deposition and CMP) is then easier, as the step to cover is reduced. Special attention must be paid to removing oxidation and pre-cleaning the trench sidewall to prevent parasitic conduction at the edge of the transistor. Sidewall conduction drastically increases the off-current of the transistor and consequently, the stand-by current of the circuit, leading to an undesired hump in the I-V curve (Fig. 1).
Complete dielectric isolation directly affects the layout of cells in a circuit. In CMOS circuits, a compact design requires groups of NMOSFETs or PMOSFETs to be placed in the same well, whereas SOI CMOS does not have this constraint, enabling N and PMOSFETs to be placed anywhere, in a random fashion. Furthermore, no n+ to p+ minimum distance between adjacent NMOSFETs and PMOSFETs needs to be defined in SOI CMOS, as no latch-up can occur because there is no parasitic thyristor structure. When a silicide layer (TiSi2 or CoSi2) is formed on the source/drain regions, NMOS and PMOS can be directly connected, forming a very compact layout.
In a single transistor, the internal substrate (also referred to as the SOI silicon layer or the body of an SOI transistor) is not accessible and cannot be externally biased, as the transistor is buried in an oxide shell. As shown in Fig. 2, the p-type and n-type bodies of NMOS and PMOS transistors, respectively, are isolated from the other terminals (source, drain and gate) and because of the buried oxide SOI substrate, the p- and n-type bodies are isolated from the bulk substrate. This creates a "floating-body" effect that governs transistor behavior.
Isolation between transistors can be suppressed if a partial lateral isolation process is used, requiring careful control of the trench depth. This can be done with a two-step STI process: A first trench is time-etched (the etch must be stopped within the silicon film before reaching the buried oxide), and a second trench goes down to the buried oxide and provides the isolation between NMOS and PMOS (Fig. 3). This process allows the bodies of the SOI transistors to be biased like bulk transistors, enabling select definition of circuit parts without creating floating-body effects. A narrow silicon thickness and a high doping level below the partial trench are needed to minimize body potential and uncontrolled floating-body effects. While this is a more complex SOI process, it offers compatibility with bulk design.
 Figure 1. Parasitic conduction at the edge of the transistor may produce an undesired hump in the I-V curve. |
The SOI MOSFET transistor is fully depleted when the depletion region below the gate covers the entire silicon film, so all mobile carriers are expelled from this electric field-dominated region. Conversely, the transistor is partially depleted when the depletion region does not extend to the whole silicon film. The degree of depletion depends on many factors, such as silicon film thickness and doping level, gate length, bias conditions, gate and buried oxide interface charges, gate work function, and substrate doping level, which affects the flat-band voltage. Depending on these variables, a given transistor may operate as a fully or partially depleted transistor.
Partially depleted operation can occur at any operating region (any bias point) and under any conditions (full temperature range) by selecting a thick enough silicon film to prevent full depletion of the smallest transistor (minimum gate length), once the doping level has been chosen to fix the threshold voltage. Fully depleted operation, however, cannot be achieved and maintained when the transistor goes into accumulation (Vgs <0 for NMOS). Therefore, to avoid inadvertent transitions from partially to fully depleted as the transistor switches from off to on, a fully depleted condition must be met when the transistor is off.
Partially depleted MOSFETs
Thin-film partially depleted SOI technologies are being widely adopted for high-speed digital applications. These technologies are similar to bulk technologies, which may be used as a starting point by first adjusting the SOI silicon thickness to the bulk drain/source junction depths. As the SOI silicon thickness is limited to 100-200nm, some implant conditions, such as dose and energy conditions, must be modified to control 2-D effects (short-channel, reverse short-channel, and drain-induced barrier lowering — DIBL) that affect the threshold voltage. Rapid thermal anneal (RTA) must be slightly modified (typically 30°C less than in bulk processes) to account for the buried oxide, which acts as a thermal barrier. Oxide thermal conductivity is about 100 times lower than that of silicon. In-line control procedures must be adapted to the SOI substrate, including defect count, ellipsometric measurements of layer thickness, and overlay-control structures. The ellipsometric measurement of a given deposited top layer needs to describe all the sub-layers, a silicon/buried oxide/silicon stack. A self-aligned silicidation process (salicidation), identical to bulk, can be implemented; but as the inter-diffusion between a metallic (Ti or Co) deposited layer and silicon takes place during salidation, consumption of the entire SOI silicon film must be prevented. A high source/drain series resistance may arise from dopant consumption under the spacer region (see SEMs on p. 63).
 Figure 3. Partial shallow-trench isolation in a CMOS SOI structure isolates NMOS and PMOS transistors formed in the SOI silicon layer. |
The electrical characteristics of a partially depleted MOSFET differ from those of a bulk MOSFET due to the floating-body nature of the device (Fig. 4). At a high-drain voltage, mobile carriers have enough energy to ionize silicon atoms in the drain region, thus creating electron-hole pairs (impact ionization). With bulk NMOS, electrons flow through the drain terminal, and holes are evacuated by the substrate, yielding the known substrate current. In the case of SOI, the holes are stored in the body (the SOI silicon layer between source and drain) as there is no external contact; consequently, the forward-biased body potential increases, and the threshold voltage decreases. This is known as the "kink" effect observed on I-V curves.
Due to its internal npn or pnp structure, a parasitic bipolar transistor is formed in parallel to the MOSFET. In an SOI MOSFET, the body is forward biased (which never occurs in bulk MOSFETs) and this bipolar transistor is activated. Therefore, the drain current increase observed for SOI transistors results from the lowered threshold voltage and the activation of the bipolar transistor. When Vgs increases, impact ionization further increases, as does the resulting body potential Vbs, which becomes a function of Vgs. The sub-threshold swing is then lower than the ideal 60mV/decade. A direct consequence of the lower threshold voltage is an increase of the off-current. Comparing bulk to SOI for the same off-current at room temperature, SOI DC drivability is higher because the threshold voltage is further reduced as Vgs increases. At higher temperatures when the off-current becomes compromised by junction leakage, the buried oxide of SOI devices suppresses the bulk wafer component. The source- and drain-to-body junctions are only perimetric junctions at the gate edge; the corresponding area is much smaller than that of bulk source/drain-to-substrate junctions.
The aforementioned floating-body effects are DC (or static) effects. To gain a complete understanding of a partially depleted transistor's operation, transient behavior must be analyzed. For example, the transistor may also be likened to a capacitive network in which the body is seen as a floating node capacitively coupled to the other terminals. Any switching signal applied to one of the terminals results in a body-potential variation. This dynamic variation is superimposed on the DC steady-state level and is responsible for the propagation delay of a given logic gate. The body potential can then vary at low drain voltage even when there is no impact ionization during switching of the terminals.
IBM has demonstrated that this effect represents a small part of the possible fluctuations of propagation delay due to variations in temperature, supply voltage, and process margins [1]. While the small area of the lateral source/drain-to-body junctions makes capacitive components, CSB and CDB, smaller with respect to bulk devices, these components increase when the body is forward biased, under impact ionization, and during transient effects. The capacitive coupling is beneficial, however, when the transistor switches off/on or on/off. In the latter case, the body potential is decreased (toward negative values for NMOS), the threshold voltage is increased, and the transistor is more efficiently blocked. Parasitic capacitances related to the bulk substrate (CSE, CDE, CBE) are MOS capacitors, which have a maximum value corresponding to the buried oxide capacitance. These can be neglected, since a thick buried oxide, typically 400nm, is used.
A consequence of the forward body bias is a reduction of short-channel and DIBL effects. The depletion charge is reduced by the positive Vbs bias, attenuating the charge sharing with source and drain. This feature emphasizes the advantage of partially depleted devices when scaling down the gate length.
Fully depleted MOSFETs
Implementing fully depleted MOSFETs in advanced deep-submicron CMOS technologies requires an ultrathin silicon film of <40nm. Such a thin silicon layer is necessary to optimize the devices, as 2-D effects are dependent on the silicon thickness. Since every cleaning and oxidation step consumes some of the silicon, the film thickness must be carefully monitored during the processes. Lateral isolation processes must also be carefully controlled because of the ultrathin silicon film. Additionally, raised source-drain regions must be implemented to contact the transistor.
Two techniques have been developed. In the first one, the silicon is thinned down to the desired thickness, the gate is patterned, and a selective silicon epitaxy is achieved to raise the source/drain regions [2]. In the second technique, the silicon film is locally thinned down to the desired thickness by using a sacrificial local oxidation. The resulting structure is known as a recessed channel (see SEMs on p. 63). The drawback of the recessed-channel technique is that the gate is not self-aligned, so tight overlay control is required to ensure that the gate remains on the flat part of the thinned region.
Implementing fully depleted technology adds some complexity to the process, but the added difficulty will be negligible as junction depths become too small for direct contacting and silicon selective epitaxy techniques are required for advanced bulk CMOS technologies.
Fully depleted devices have garnered strong interest because of their electrical characteristics [3]. The equivalent capacitive network is a powerful tool for understanding the operation of the fully depleted MOSFET. Due to the full depletion of the silicon film (Csi is the equivalent capacitance), the gate is directly coupled to the substrate. The weak inversion slope, which characterizes the drain current variation in the sub-threshold regime, is defined by:
 |
null
where Φ s1 and Vg are the surface and gate potentials, respectively, Cox1 is the gate oxide capacitance, and Cox2 the buried oxide capacitance. The sub-threshold swing is defined as S = 2.3nkT/Q, where k is Boltzmann's constant, T is temperature, and Q electron charge. For a thick buried oxide, Cox2 can be neglected and n is approximately 1. Since the sub-threshold swing is related to the weak inversion slope, n, S then takes the ideal 60mV/decade value.
The main advantage of a fully depleted device is that this low sub-threshold swing enables a lower threshold voltage for a given off-current. As the silicon film is fully depleted, there is no junction capacitance between the body and source/drain. A fully depleted gate has a much lower output capacitive load than a partially depleted or bulk one, which contributes to enhanced gate switching speed and decreased power consumption.
The fully depleted operation can be clearly observed by plotting the variation of the threshold voltage against the substrate potential (the substrate becomes a back gate). Due to the capacitive coupling, the threshold voltage linearly varies with the back gate bias, while the slope is equal to a (also called the coupling factor). This factor reduces to Cox2/Cox1 to equal the oxide thickness ratio of Tox1/Tox2 for a thick buried oxide.
The full depletion condition can be suppressed by accumulating or inverting the silicon/buried oxide interface (back interface). This can be done by varying the back-gate voltage to impose inversion or accumulation at the back interface. The threshold voltage of a fully depleted transistor depends on the silicon thickness, the doping level of the silicon film, the gate oxide thickness, and the flat-band voltage. By reducing the doping level as much as possible, sensitivity of the threshold voltage to the silicon thickness variation is attenuated. This requires that an approximately mid-gap gate material be used to obtain a reasonable threshold voltage of about 0.3V.
Fully depleted devices do not exhibit floating-body effects as long as the full depletion is effective. The impact ionization mechanism may reduce full depletion through the injection of majority carriers into the body. In this case, a slight kink effect may be observed on the I-V curves (Fig. 5); the device is fully depleted at low Vds and displays partially depleted behavior at high Vds and especially at low Vgs.
For deep-submicron devices, the control of 2-D effects is achieved by thinning both the silicon and buried oxide, but the advantage of the low buried oxide capacitance may be lost. A maximum silicon thickness of 20nm is needed to optimize a 0.1µm gate-length device. The greatest challenge for such devices is to minimize the source/drain series resistance to maintain a high drivability, which also requires efficient monitoring of the silicon thickness.
Modeling and circuit simulation
An SOI design requires the use of a circuit simulator, such as SPICE, to describe accurately the electrical behavior of the devices. An existing bulk model can be adapted for fully depleted devices by modifying the threshold voltage and charge equations to account for the relationship of the depletion charge to silicon thickness. Modeling of partially depleted MOSFETs is more complex and will be described.
An SOI partially depleted model includes a bulk MOSFET model where the substrate current corresponds to the impact ionization current, which affects the body potential. The junction currents must be accurately predicted, as the body potential results from a balance between impact ionization and body/source junction currents at high drain voltage. The drain current, in turn, results from both the MOSFET and the parasitic bipolar currents, so the bipolar transistor also must be accurately modeled.
Each of the current and charge equations must include a strong forward bias of the body. Threshold voltage variation with the body potential must also be accurately predicted in both forward and reverse modes. The body potential is not computed by the model itself but is solved by the SPICE simulator, where the body is entered as a floating node. From the balance of all the current components flowing into the body — impact ionization, gate-induced drain leakage (GIDL), junctions, and gate tunneling — the body potential is determined. Figure 6 shows the equivalent circuit of a partially depleted MOSFET transistor.
Several SOI models already exist: BSIMSOI [4], SOISPICE [5], STAG [6], and LETISOI [7]. The first three models were developed by universities and are in the public domain. BSIMSOI and SOISPICE address both fully and partially depleted devices. Circuit designers must evaluate the different models to fit their needs, such as simulation speed, accuracy, and convergence. LETISOI was developed at the Laboratoire d'Electronique, de Technologie de l'Information (LETI, Grenoble, France), an electronics industry R&D laboratory, and demonstrated on its internal 0.25µm CMOS/SOI technology. This model is dedicated to partially depleted devices.
Using an SOI model helps one understand the behavior of the SOI transistor. The kink effect must not be seen as merely a static effect, as the body charge due to impact ionization progressively builds up. Consequently, the kink effect depends on the sweeping rate. Further, the drain voltage is ramped up with different slew rates. Therefore, when the drain switches very fast, the charge does not have enough time to build up, and there is no kink. The kink effect is frequency dependent.
In dynamic operation, the body potential is linked to the switching signals applied to the other terminals. At any given time, it depends on the previous states of the device (the history effect). Using a switching inverter, the body potential of the N and PMOS structures will vary from its initial state, fixed by the DC condition, to a steady state. This variation depends on the clock frequency and the duty cycle. Once the steady state is reached, the body potential no longer depends on the initial DC condition. The propagation delay also varies until the steady-state condition is established. The variation range, which is less than 10% of the mean value, is also related to the features of the technology. An optimized SOI circuit design can be achieved if an SOI model is used to predict the influence of the related body effects on gate performance.
Conclusion
SOI MOSFETs offer an intrinsic low-threshold voltage, an advantage when designing low supply-voltage and low-power circuits. SOI opens possibilities for a variety of devices: dynamic threshold-voltage MOSFET (DTMOS) for ultralow-power, double-gate transistors in sub-0.1µm devices. With high-resistivity SOI substrates, mixed RF-digital functions can be processed, integrating high-quality passive components. Basic process improvements and better choices of starting silicon wafers have made possible these improvements and will further enhance the development of SOI devices.
Acknowledgments
The authors wish to thank the Laboratoire d'Electronique, de Technologie de l'Information (LETI) for its contribution.
References
- G.G. Shahidi, et al., ISSCC, p. 426, 1999.
- C. Raynaud, et al., SSDM Proceedings, p. 150, 1997.
- J.L. Pelloie, Y-C. Sun, Sixth International Symposium on SOI Technology and Development, ECS meeting, p. 263, 1994.
- www.device.eecs.berkeley.edu/~bsimsoi/
- www.soi.tec.ufl.edu
- www.micro.ecs.soton.ac.uk/stag
- J.L. Pelloie, et al., European Meeting on SOI Development, Granada, Spain, 2000.
Jean-Luc Pelloie is chairman and a co-founder of SOISIC. He holds three patents and has authored and co-authored more than 100 technical papers. SOISIC, 15 rue des Martyrs, 38054 Grenoble Cedex 9, France; ph 33 4 38 78 40 05, fax 33 4 38 78 66 18, e-mail [email protected].
André Auberton-Hervé is a member of the IEEE and of the Electrochemical Society. He co-founded SOITEC in 1992. Auberton-Hervé has 17 years of experience in SOI technologies.