Simultaneous optimization of electroplating and CMP for copper processes
11/01/2001
Gautam Banerjee, Rodel Inc., Phoenix, Arizona
Joseph So, Rodel Inc., Newark, Delaware
Bob Mikkola, Shipley Co. LLC, Marlborough, Massachusetts
overview
Electroplating copper from various sources using different additives results in different surface film chemistries. During subsequent polishing, the post-CMP results such as removal rate, dishing, erosion, and surface defects can vary widely, even if identical sets of CMP consumables and parameters are used. Simultaneous optimization of plating and planarization processes can enable the best post-CMP results, and thus yield.
Decreasing device geometries offers challenges when integrating new materials into the process flow. For feature sizes 0.18µm and below, the properties of copper have made it a natural selection for interconnects. Since the familiar physical vapor deposition (PVD) and chemical vapor deposition (CVD) techniques cannot produce the necessary uniform coverage at these dimensions, electroplating has become the method of choice for depositing copper interconnects [1].
Simultaneous optimization
Although copper electroplating is an established technique, the ability to fill trenches and vias in a uniform manner has been the focus of research and development for only a few years. Due to its importance in IC manufacturing, many corporate research centers are engaged in developing appropriate Cu electroplating formulations and processes. It has been found that differences in Cu plating methods lead to different types of plated surface morphologies. It has also been found that even with identical process conditions and consumables, CMP results differ with different surface morphologies, making it difficult to predict the type of defects that may be present on post-CMP wafer surfaces.
Copper CMP is a relatively immature process. Therefore, close control of the plated film is necessary to minimize the amount of overpolish required and subsequent dishing and erosion. Further, controlling the thickness profile to ensure wafer-to-wafer repeatability is needed to fine-tune the CMP process [2].
In order to establish a logical correlation between the results of electroplating and CMP of a given set of wafers, the interdependency of the two processes has been systematically studied. We have established that the best post-CMP results can be obtained when both the electroplating and CMP chemistries and processes are optimized together.
Experiment
In this study, patterned wafers using Sematech 854 and 931 photomasks containing isolated lines and dense structures with 5000Å and 7000Å trench depths, respectively, were electroplated with two different plating compositions developed in-house. A 5000Å thermal oxide/250Å Ta/1000Å copper seed stack was deposited on each wafer before being immersed in the electroplating bath. The tantalum (defined as the barrier layer) and seed layers were deposited using PVD. Two additives (accelerator and suppressor) were added to the base electrolyte of one of the plating compositions. The other composition had a third additive, a leveler, used to level the plated surface as much as possible.
Copper films, approximately 15 KÅ thick, were electroplated in a cleanroom environment with a Semitool Equinox system using a multistep DC current waveform. The electroplated film was held at room temperature for several days (self-annealing) to permit the grain growth transients to stabilize prior to CMP operations.
 |
After plating, the wafers were characterized using focus ion beam microscopy (FIB), atomic force microscopy (AFM), optical microscopy, and surface resistivity. CMP was performed on Applied Materials' Mirra polisher, using specially formulated slurries and reactive liquids, and two different kinds of polishing pads. A two-step CMP process was performed. The first step removed the top copper layer while the second removed the barrier layer, in this case, Ta. The wafers were then cleaned with DI water and a Lam Synergy cleaning system. Defect studies were then performed on a KLA-Tencor AIT-1, a Leica optical microscope, and a Veeco Dimension Vx-210 Atomic Force Profiler.
Results and discussion
One set of wafers was plated in baths containing leveler chemistries and a second set of wafers was plated without. Shown in the FIB images in Fig. 1, the addition of a leveler to the plating solution clearly minimized the overburden topography. Further comparisons shown with AFM images (Fig. 2) and data (Table 1) support the FIB results: Plating chemistries containing a leveler significantly reduced topographical undulation. The Rmax (defined as the difference between the highest and lowest points on the surface relative to the mean plane) without the leveler was ~787nm and with the leveler, ~22nm.
The resultant surface was expected to facilitate the removal of Cu during CMP, minimize dishing, and reduce the number of defects.
CMP was performed on the set of plated wafers. The post-CMP results presented are based on wafers patterned with the 931 mask. Figure 3 shows a typical rate of copper removal during the first CMP step for wafers plated with both types of chemistries. The wafers plated with the leveler chemistry showed an initial removal rate of approximately 9000Å/sec before stabilizing to about 7000Å/sec.
In comparison, wafers plated without the leveler chemistry showed a lower polishing rate and an increasing trend from 3800 to 4200Å/sec during the same 30- to 90-sec time frame. This suggests that an optimized plating chemistry can aid in improving copper removal rates during CMP.
The improved copper removal in the presence of a level, as-plated surface was also illustrated through FIB images (Fig. 4). The as-plated surface had a 4000Å copper overburden over a 10µm-wide, copper-filled trench.
The first CMP removed 1.3µm of copper overburden from the flat field, but only 0.7µm over the dished area of the trench. Polishing was calculated to be 1.86x faster on the flat field. Finally, AFM data (Table 2) show a reduction in surface roughness after 60 sec of polishing when leveler chemistries were used.
 Figure 6. Variations of trench height with time were smallest when concentrations of leveler were optimal, in this case, at the highest level. |
The variation of trench height with time is indicative of planarization efficiency. The effect of plating chemistries and the flatness of as-plated surfaces on trench height variations across the wafer is shown in Figs. 5 and 6. The wide difference in trench height variation shown in Fig. 5 indicates poor planarization effectiveness.
In an attempt to optimize the plating solution composition, leveler concentrations were varied from zero (No), to low and moderate, to optimum. As indicated in Fig. 6, planarization efficiency was greatest at an optimum leveler concentration, which, in this case, was the highest level tested and the flattest, as-plated surface.
Following the first CMP step, a correlation between the amount of residue and the plating chemistry was determined. Again, a level, plated surface was shown to be desirable.
The plating chemistry with leveler left no copper residue, whereas the other plating chemistry left a considerable amount under identical polishing conditions (see Figure 7). To remove all residual copper on the isolated lines and dense structures on the post-CMP wafers, polishing chemistries and pads were optimized along with the plating solutions.
Post-CMP cleaning
No CMP experiment would be complete without post-CMP cleaning. In addition to a DI wash, four different post-CMP cleaners from different vendors were used to optimize the post-CMP results.
 Figure 8. After 1st- and 2nd-step CMP, a) BTA residues remained on the wafer surface, but b) were subsequently removed with a proprietary cleaner. |
Because of the improvements obtained from using the plating solution containing a leveler, for this set of experiments, all the wafers were plated with leveler chemistry only. The different clean chemistries were used on wafers plated and polished under identical conditions. All the defect characterization work was done on a Leica optical microscope using three die areas. Defect analysis results are shown in Table 3.
Figure 8 shows a typical problem after CMP — BTA (benzotriazole) residues. If BTA removal is the goal, then Cleaner B was the clear winner. The quantification of %BTA was on a relative scale. No mass spectra or IR spectra were used to chemically characterize BTA.
 |
BTA particles, however, are very distinct from plating defects and scratches, and were therefore identified before and after cleaning with optical inspection. While DI water performed better than most in residual copper removal and pattern defects, a 3% BTA residue following post-CMP cleaning was our best result, using simultaneous optimized plating and CMP processes.
Conclusion
An effective copper CMP process depends on the optimization of all the consumables, including the plating, polishing, and post-CMP cleaning chemistries. All three factors are completely interdependent; individual testing of the efficiency of each one may or may not yield the best results.
 |
In this study, the addition of a leveling compound to the plating chemistry, the use of two different polishing pads, and a proprietary cleaning chemistry, as well as optimized plating, polishing, and cleaning process parameters helped achieve the best surface finish on two differently patterned wafers.
Acknowledgments
The authors gratefully acknowledge the contributions of J. Calvert, J. Rychwalski, E. Najjar, Shipley, and T. Thomas, H. Porter, Rodel, which support the results presented in this article.
Equinox is registered to Semitool Inc.; Mirra is a trademark of Applied Materials; Synergy is a trademark of Lam Research Corp.; and Dimension, Vx, and Atomic Force Profiler are trademarks of Veeco Instruments Inc.
References
- M.E. Gross, C. Lingk, W.L. Brown, R. Drese, "Implications of Damascene Topography for Electroplated Copper Interconnects," Solid State Technology, Aug. 1999.
- V. Shannon, D.C. Smith, "Copper Interconnects for High-Volume Manufacturing," Semiconductor International, May 2001.
Gautam Banerjee received his MS in chemistry (1986) from the Indian Institute of Technology at Kharagpur, India, and his MTech/PhD in corrosion science and engineering (1988/1992) from the Indian Institute of Technology, Bombay. He has been executive, R&D, for VIP Industries Ltd., Nasik, India, and has more than 25 publications. Banerjee is the project leader of the MOSAIC EPCu-CMP integration program at Rodel Inc., 3804 E. Watkins St., Phoenix, AZ 85034; ph 602/431-0500; fax 602/431-0200, e-mail, [email protected].
Joseph So was a process engineer at Advance Development Group (ATG), National Semiconductor, before joining Rodel. He is an application engineer at Rodel, responsible for developing copper consumable sets, including integration of copper electroplating and CMP.
Bob Mikkola received his BS in chemistry in 1977 and his MS in physical chemistry in 1980 from Michigan Technological University. He has worked at Martin Marietta Energy Systems, Sematech, and Motorola. As program manager for the MOSAIC Copper R&D Group at Shipley, he is responsible for the development of copper electroplating chemistry and techniques for use in gap fill of advanced interconnects.