Developments at IMEC

10/01/2001

IMEC, based in Leuven, Belgium, is Europe's leading independent microelectronics and ICT R&D center. It has been very active recently, with a spate of studies and joint programs. Here we outline some of the most interesting developments.

Studying the limits of CMOS technology
IMEC has launched a study to determine the practical limits of the semiconductor industry's workhorse manufacturing process technology, CMOS.

The IMEC industrial affiliation program (IIAP), called the Advanced Device Implementation Program, will determine whether CMOS can be improved to perform at semiconductor gate lengths from 45nm to 22nm. While current theory estimates that conventional CMOS will no longer be a viable mass manufacturing process technology at sub-50nm gate lengths, it is possible that the technology may be scalable even below 45nm.

The typical problems of controlling short-channel effects while maximizing performance are the main obstacles of scaling CMOS, but the constraints on device design for sub-45nm CMOS devices are much more severe and therefore require innovative solutions with new materials and/or device architectures.

The 3-year Advanced Device Implementation Program for sub-45nm devices will identify the most critical limitations of scaling conventional CMOS, while also investigating potential advanced or alternative solutions for further improvements of silicon-based MOSFET technology. The main target is to provide clear indications about the most likely architectures for the 60-30nm technology nodes as mentioned in the latest version of the International Technology Roadmap for Semiconductors (ITRS).

CMOS experiments will focus on front-end-of-line (FEOL) manufacturing issues such as gate stack, channel/substrate engineering, shallow junction formation, spacer technology and silicidation. A major part of the IIAP program is being devoted to the device implementation of high-k materials and metal gates for ultrasmall gate dimensions. The program also includes the support of advanced simulation tools and state-of-the-art characterization techniques.

IMEC and Philips Research's 100nm CMOS devices
IMEC and Philips Research have announced that the first functional 100nm CMOS devices have come out of IMEC's cleanroom facility, achieving electrical performance that meets the requirements of the ITRS. IMEC and Philips Research went into a strategic alliance beginning in 2000 to explore the key processing and integration steps required for 100nm CMOS technology. The technology is based on a scaled-down version of planar CMOS (such as at the 130nm node) and is being optimized for both low-leakage and high-performance applications.

To scale the existing processing steps to the 100nm node, the gate stack was optimized, with special attention to the development of new gate dielectric recipes, and source/drain engineering was performed using ultralow-energy implantation and super HALOs in conjunction with spike anneal. Advanced cobalt salicidation based on a Ti-capping layer has been integrated for further progress of the technology node. Nitrided oxides were optimized to reduce gate leakage and to have better immunity to boron penetration. Significant improvements in device performance were obtained by thinning the gate dielectric from 2nm to 1.5nm.

Drive currents of 840µA/µm for NMOS and 350µA/µm for PMOS were obtained at VDD=1.2V and an off-state current of 20nA/µm. "The achieved electrical performance meets the ITRS requirements and demonstrates that a successful first step has been made in the joint exploration of 100nm technology at IMEC and Philips Research," say Prof. Gilbert Declerck, president and CEO of IMEC and Dr. Carel van der Poel, VP of Philips Research. Regarding further integration of the 100nm front-end process, a major effort is being devoted to both FEOL modules, including copper interconnects and low-k dielectrics, and shallow trench isolation scaling.

Program on alternative devices in CMOS
Another IMEC program will investigate alternative devices that can replace conventional CMOS transistors. Codenamed EMERALD, for emerging alternative devices, the IMEC industrial affiliation program (IIAP) will identify new device structures that will overcome the limits of classical CMOS transistors below 35nm.

At sub-35nm process geometries, CMOS based on classical devices may reach its limits as a viable mass-manufacturing industrial technology. Anticipating that era, IMEC will explore innovative manufacturing processes, materials, and/or device architectures that will be required to overcome major bottlenecks in next-generation manufacturing processes.

The EMERALD IIAP will investigate technologies that have emerged in prior IMEC studies and have shown strong potential for future mass manufacturing technologies beyond classical CMOS. These include fully depleted silicon-on-insulator; high-mobility CMOS based on strained silicon/silicon germanium (Si/SiGe) layers; vertical devices; and double-/triple-gate and gate-all-around devices. Compatibility with current CMOS technology and transitional capabilities from conventional CMOS will also be investigated. In addition, the EMERALD IIAP will attempt to determine complexity levels of each process alternative.

IMEC ramps 0.18µm BiCMOS program
IMEC has begun a two-year program to develop a 0.18µm BiCMOS manufacturing process that will ease the manufacture of radio-frequency (RF) devices. The goal of the program is to develop a manufacturable, fully integrated 0.18µm BiCMOS process technology specifically for 2- and 5-GHz RF applications, with emphasis on the combination of low power and high performance. Specific attributes of the manufacturing process include — besides a silicon germanium carbon (SiGeC) bipolar device — a core CMOS process with an n+/p+ analog 0.18µm technology, featuring shallow trench isolation, 3.5nm gate oxide thickness and cobalt-salicide.

IMEC CEO Declerck said, "RF technologies are essential to the success of next-generation wireless communications applications, including networks like Bluetooth. This program will work to ensure that efficient manufacturing technologies are in place to support the most advanced products designed exactly when they are needed."

The BiCMOS process will utilize a SiGeC heterojunction bipolar transistor (HBT) to attain superior RF performance at low current densities. The HBT consists of a quasi self-aligned emitter/base architecture with SiGeC base, deep trench isolation, and in situ arsenic doped poly-emitters. The technology will initially run in IMEC's 200mm manufacturing pilot line with a copper/oxide back-end, and includes different types of poly resistors, double poly capacitors, varactors, inductors and double metal capacitors.

Structured as a three-part development program, IIAP milestones include HBT module development, BiCMOS process integration, and RF passive components.

During the first year, the main activities will be concentrated on design of a test chip for process development, process step and module development, and process assembly. The second year will focus on solving integration issues to achieve a fully integrated 0.18µm BiCMOS process by the end of 2002.