Devices dictate control of implant-beam incident angle
10/01/2001
Ukyo Jeong, Jian-Yue Jin, Sandeep Mehta Varian Semiconductor Equipment Assoc., Gloucester, Massachusetts
overview
As device scaling continues, precise control of dopant placement becomes a critical requisite in the fabrication of high-performance devices. Here we compare the performance of single-wafer parallel-beam implanters to traditional batch implanters, with spinning disks, looking at beam incident angle control. There are several sources of beam incident angle variation in batch implanters, depending upon the scanning system and beam delivery mechanism. The consequences of these sources of angular variations are crucial in high-performance device fabrication.
From an ion implant perspective, the consequence of continued CMOS device scaling involves numerous challenges. Doping technology, more than any other process step, controls the ability to achieve overall parametric goals of device scaling. The control of the dopant placement and concentration accommodates large drive current in minimal device dimensions and the suppression of leakage current to meet overall power consumption limits and thermal budget of a circuit.
As a consequence, one of the most critical aspects to the continued miniaturization of devices implies an increase in doping concentration at and beyond the levels allowable by the law of thermodynamics of silicon. Amazingly, the progression of this increase shows a >100x enhancement over the past 20 years in doping concentration [1]. While a number of efforts are under way in the industry to address this solid solubility limit problem, meeting the increased doping concentration requirement is only a part of the challenge.
Of almost equal importance for ion implantation is addressing repeatable and uniform placement of the dopant, formation of tightly controlled channel-to-well profiles, and obtaining the lateral abruptness of the source-drain extension junction into the channel. These challenges are directly related to ion beam incident angle control. Single-wafer systems by their very nature are designed to address the beam angle control necessary for sub-130nm technology nodes. Unprecedented in device scaling history, the issue of total beam incident angle control must be addressed for a range of implants — from high current through medium current and high energy — if the industry is to proceed successfully to the sub-100nm realm.
Beam incident angle
For the last 30 years, controlling beam incident angle in ion implantation was not considered to be a critical factor in planar device fabrication. This is no longer the case. While the device structure has been literally planar, transistors have been constructed with much larger lateral dimensions than height or depth dimensions. Continued emphasis on using silicon real estate more efficiently, however, has accelerated the need to scale lateral dimensions more rapidly than vertical dimensions. As a result, parametric performance becomes more governed by three-dimensional effects of shadowing and asymmetry that are directly associated with the placement of the dopant [2].
There are several sources of inaccuracy in dopant placement and beam incident angle control in traditional spinning-disk batch implanters. Batch implanters use a concave-shaped disk to secure wafers in their respective sites during the high-speed spin motion of the disk. Centrifugal force exerted on wafers against the disk surface holds them in place. Since the conical disk has a curved surface and a wafer surface is flat, this leads to a beam incident angle variation across the wafer during the implant process. Depending on the dimensions of the disk, cone angle, and wafers, this can amount to ±1.5° of variations across a wafer.
Another inaccuracy of beam incident angle comes from the rotation of the disk and wafers. During disk rotation, wafers rotate at the same angular velocity as the disk. This means the azimuth angle of the wafer does not remain constant during the process. The azimuth angle changes as the wafer moves across the beam path to cause implant orientation angle changes across the wafer. For a typical 13-site disk, the angle of the wafer changes from -13 to +13° for each wafer.
As a result of the combined effects of tilt and azimuth angle variations (i.e., tilt and twist), the beam incident angle does not remain at recipe-prescribed values, but passes over a range of angles during an implant. This produces an inherent set of major and minor channeling axes for all batch implanters (Fig. 1). It is these variations that contribute to alteration in device parametrics now being noted in advanced technology node development. However, single-wafer ion implant systems are completely free from either of these effects, since no disk is used to contain and position the wafer during implant.
Well doping
The consequence of such large inherent variations of beam incident angle in batch implanters leads to a limited applicable set of implant angles for advanced semiconductor device fabrication. For example, 7°-tilt and 22°-twist implants have been widely practiced in most well-implant processes to achieve the best doping uniformity across the wafer. However, as device geometry scales down, the 7° tilt is large enough to create an implant shadowing effect and thus limit the opportunity to further increase transistor-packing density.
Shallow trench isolation (STI) enabled by chemical mechanical polishing (CMP) is one of the great evolutions in well-to-well isolation technology. Thanks to CMP, excellent-quality isolation can be achieved without lateral infringement problems that are observed with LOCOS techniques. However, while STI has paved the way for fine patterning of active and field areas, ion implant shadowing has become a major inhibitor in further device scaling optimization. For example, in well-doping applications, implant energy has been confined to the mid-high energy regime, mostly due to requirements for junction capacitance reduction, while the design rule of the device has been shrinking rapidly. This implies that masking photoresist thickness has been kept constant through many generations of device design rules.
 Figure 3. RBS yield as a function of the incident angle for 1.5 MeV B+ into <100> silicon. |
In a 7°-tilt implant process, a 2µm photoresist mask can result in a maximum 0.25µm of shadowed area at the boundary of the photoresist mask. A margin for resulting implant shadowing must be taken into consideration during mask layout for STI and wells. As the minimum design rule shrinks, such a margin is an unnecessary consumption of silicon real estate, impeding packing density, and interconnection efficiency.
Reducing the implant tilt angle is obviously the simplest solution for the problem. However, this was not a practical choice until the advent of single-wafer parallel beam implanters. The reason for the previous limitation is a direct consequence of the batch implanter process. Dopant placement accuracy in spinning disk systems is severely compromised from nonuniform channelings.
To avoid the deep channeling axis with 0°-tilt implant, device manufacturers have used reduced tilt angles. A 3°-tilt implant can be a potential choice as it reduces the shadowing area to half, while maintaining doping profiles similar to 7°-tilt implant. However, if a 3° implant is performed on a batch implanter, it is still affected by the tilt angle variations described earlier (Fig. 2). This makes the process of batch implantation impractical for obtaining the doping uniformity required for advanced technology nodes.
We explained this sensitivity of the doping profile to a small variation of beam incident angle in a Rutherford backscattering (RBS) experiment (Fig. 3). The data show RBS counts as a function of beam incident angle into a <100> silicon wafer for a 1.5MeV boron ion beam. The number of RBS counts drops significantly as the incident angle decreases, indicating a large change in channeling characteristics.
Halo doping
Halo implants are commonly used in CMOS device fabrication. These implants usually require 30-45° tilt angles to place dopants deep underneath the gate electrode. At these large tilt angles, the channeling behavior is very different from that of a small tilt angle implant. There are many more planar channels at larger tilt angles than 7° within a certain twist angle range. For example, a rotation from twist 0° to 45° at 7° tilt only passes one {620} planar channel, plus the {004} at 0° twist and the {220} at 45° twist. On the other hand, the same twist angle rotation at 35° tilt can pass 6 planar channels — {311}, {422}, {620}, {242}, {331}, and {131} — plus the {004} at 0° twist and the {220} at 45° twist [4].
As previously discussed, conventional batch implanters have twist angle variations of ±13° during the process. For a 7° tilt, the {620} planar channel can still be avoided by selecting twist angle for ~32°. However, for a large tilt angle, because the number of planar channels per twist angle is much higher, it is inevitable to have one or several planar channels on the wafer, resulting in dopant profile nonuniformity. Therefore, a batch implanter cannot be an adequate tool for these applications. However, the halo implant requires tight control and careful consideration of both the tilt and twist angles. Using TCAD simulation, some have reported that 1° tilt angle variation will induce significant Vt variation [5]. Others have reported that a ±2° tilt angle variation can cause up to 5% Vt change and 60% leakage current change in 180nm technology [6].
Single-wafer parallel beam implantation, with precise control of beam incident angle, eliminates the concerns mentioned above.
Source-drain extension doping
By suppressing short channel effects with minimum junction depth while allowing maximum conduction of current, source-drain extension (SDE) engineering improves the performance of a device. Optimization of these two conflicting aspects — junction depth and conductance — has driven process technology to its extreme edges. Low-energy ion implantation and dopant activation methodologies are aligned to achieve a common target: maximum conductance and minimum depth of the junction.
Recent studies, however, show that sheet resistance of the SDE reflects only a part of the total external resistance in MOS devices. An even larger portion of the external series resistance occurs at the tip of the SDE junction into the channel inversion layer where the carrier accumulation layer transforms to the inversion layer [7, 8]. Formation of a laterally abrupt junction is critical to a resolution of the current flow bottleneck at the SDE tip. It is also reported that abruptness of the lateral junction enables scaling of the overlap between gate and SDE without losing drive current merits.
Although the gate re-oxidation process can control SDE-to-gate overlap, the junction abruptness to the channel is purely determined by lateral straggling of the implanted ions and subsequent diffusion process. Unlike mid-high energy ion implant applications, channeling effects are minimal for low-energy, high-current implants because of increased channeling acceptance angle. There is still a significant difference, however, between single-wafer and batch implanters due to the implant shadowing effects. Ideally, the 0°-tilt implant gives the most abrupt lateral junction because any tilt angle larger than 0° induces shadowed areas at the vicinity of the gate pattern, leading to laterally graded doping profiles. If the incident beam has an angular spread deviating from the ideal parallel beam, each of the ions having different incident angles will make different shadows. The result is a loss of dose and junction abruptness at the outskirts of the gate.
Spinning disk batch implanters use a stationary spot ion beam. The wafers pass through the beam due to the rotation of the disk. Especially for low-energy, high-current ion beams, a large number of slow-moving ions are crowded into a confined envelope of the beam. As a result, charged particles generate an electric field by which the ions are repelled outward from the beam. As the charge density increases, the beam develops stronger space charge potential, causing the beam envelope to expand as it moves. A simple mathematical model predicts that 5keV arsenic ions carrying 10mA of beam current can diverge >40° after traveling 10cm [9].
To study the beam incident angle spread effects on SDE doping, we modeled a typical diverging beam into a process simulation. We simulated an 80nm gate length NMOS device using TSUPREM4 and Medici. The effective channel length measured 65nm after a 2keV arsenic SDE implant and subsequent spike anneals. The beam was modeled to contain ±14° of divergence around the principal tilt angle 0°. The angular distribution of beam intensity was assumed as Gaussian. Then, the divergent beam results were compared with parallel beam results. The spread beam resulted in a laterally graded junction of SDE due to beam shadowing at the outskirts of the polysilicon gate. Figure 4 shows a lack of SDE junction doping concentration at the vicinity of the gate, along with a loss of lateral profile abruptness due to the increased lateral penetration of ions.
Device simulations performed with Medici clearly exhibit the effects of beam incident angle spread. We found that the parallel beam implanted device flows 7.5% more drain current than with a divergent beam. The primary reason for different conduction behaviors can be explained by the difference in the lateral junction abruptness and accumulation resistance of the two devices.
Our TCAD simulation results suggest that the parallel beam implanter process yields more current drive. In other words, faster circuits are obtainable by switching the SDE doping tool to a parallel beam implanter from the conventional batch implanter.
Conclusion
We have discussed why the control of beam incident angle becomes increasingly critical to aid further scaling of devices. The singlewafer parallel beam implanter minimizes beam incident angle variations. These implanters allow choice of beam incident angle without compromising doping uniformity, through a wide range of tilt angles from -60 to +60° and unlimited choice of twist angles.
In modern high-performance device fabrications, the single-wafer parallel beam implanter brings advantages to various ion implant doping applications. In addition, single-wafer systems enable large angle tilt implants for halo and pocket applications. Of most importance, process and device simulation results indicate a significant drive current and clock speed benefit for high-speed MOS devices.
References
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- D. Kapila, et al., "The Effect of Deterministic Spatial Variations in Retrograde Well Implants on Shallow Trench Isolation for Sub-0.18µm CMOS technology," IEEE SM, No. 4, Vol. 12, Nov. 1999.
- J. Ziegler, et al., "Map of High Index Axial Channels Near <100> Silicon," Applied Physics Letters, 46, 358, 1985.
- R. Simonton, Al Tasch, "Ion Implantation Science and Technology," p. 293, Ion Implantation Technology Co., Yorktown, NY, 1996.
- N. Variam, et. al., 13th International Conference on Ion Implantation Technology, September 2000, Austria.
- Babak Adibi, et al., Solid State Technology, Jan. 2001, p. 88.
- C. Osburn, et al., "Design and Integration Considerations for End-of-the Roadmap Ultra-shallow Junctions," Ultra-Shallow Junction Workshop, 1999.
- T. Ghani, et al., IEEE Symposium on VLSI Technology, June 12-14, 2000.
Ukyo Jeong received hi BS in physics from Sogang University, Seoul, Korea. He is a senior scientist at Varian Semiconductor Equipment Associates, 35 Dory Rd., Gloucester, MA 01930; ph 978/282-2142, fax 978/281-1897, e-mail [email protected].
Jian-Yue Jin received his MS in nuclear technology from Peking University and his PhD in physics from University of North Texas. He is a senior scientist at Varian Semiconductor Equipment Associates.
Sandeep Mehta received his MS and MTech in physics and solid state materials from University of Roorkee and IIT, Delhi, India. He completed his doctoral research at NASA Lewis Research Center and Cleveland State University. Mehta is a manager of strategic applications and process development at Varian Semiconductor Equipment Associates.