Stress-free polishing advances copper integration with ultralow-k dielectrics
10/01/2001
David H. Wang, Stephen Chiao, Mohammed Afnan, Paul Yih, Michel Rehayem, ACM Research Inc., Fremont, California
overview
A process that eliminates nearly all the limitations of conventional CMP has been developed. The new technique, called ultra stress-free polishing (Ultra SFP), allows a prompt process migration to low-k dielectric materials (where k < 2.2). Because this new technology does not use pads or slurries, or have the attendant conditioning time, it greatly reduces the costs associated with copper removal. It also provides another way to compensate for the increased interconnection delays incurred with progressive reduction in feature sizes.
During the past decade, the semiconductor industry has increased the performance of semiconductor devices in accordance with Moore's Law, which calls for a doubling of device density every 18 months. This improvement has been achieved, in part, by a decrease in the feature size, which has quickly shrunk from 0.25µm to 0.18µm, and now, to 0.13µm. One factor that limits performance boosts, however, is the increased signal delay at interconnects (the lines of conductors that connect elements of a single semiconductor device and/or connect any number of devices together).
As feature size has decreased and density increased, the closer proximity of circuit interconnects has increased their line-to-line capacitance, resulting in an even greater signal delay.
Interconnect delay
In general, interconnection delays have been found to increase with the square of the reduction in feature size. In contrast, gate delays have been found to decrease linearly with a reduction in feature size. When feature size shrinks to <0.18µm and beyond, speed performance of devices no longer depends on feature size, but on interconnect distance (the line-to-line distance).
One conventional approach to compensate for this increase in interconnection delay has been to add more layers of metal. Adding more layers of metal, however, has the disadvantage of increasing production costs. Furthermore, these added layers of metal generate additional heat that is detrimental to both chip performance and reliability. Recently, the industry has been exploring the use of copper instead of conventional aluminum as the interconnect metal. Copper has greater conductivity than aluminum and is also not as susceptible to electromigration. Thus, lines formed with copper are more likely to be thinner under current load than those formed with aluminum. However, the transition from aluminum to copper only improves speed performance by 30%, whereas the transition from silicon oxide (k = 4) to ultralow-k dielectrics (k = 1.5) yields a speed performance as high as 266%.
There are some well-known disadvantages to copper. One has been its tendency to "bleed" into the silicon substrate, thereby contaminating the device. Furthermore, in a typical damascene process using conventional chemical mechanical polishing (CMP), adding up to 1.5µm of the metal requires an extended polishing time and consumes a significant amount of slurry. During the CMP process, erosion and dielectric loss change the topography of interconnect layers as the number of stacked layers increases, causing lithography focus issues and yield loss. Scratches caused by large particles in slurries or broken diamond tips that get embedded in the polishing pad during the pad-conditioning process are additional uncertainties when using conventional CMP, and are detrimental to production-yield control.
From oxide to low-k dielectrics
Despite the disadvantages of CMP, it is the industry's current tool for removing copper in copper/silicon oxide damascene structures. In order to achieve significantly higher-speed performance, copper must be integrated with low-k dielectrics, and, preferably, with ultralow-k dielectrics (k<2.5). The low-k dielectric implementation strategy being used today is to gradually migrate from oxide (k = 4) to fluorinated oxide (k = 3.5), and then to low-k dielectrics with successively lower k values of 3, 2.6, 2.2, and finally, those materials with k<2.
The multistep low-k implementation strategy described above is costly, high risk, and gives IC manufacturers a great deal of uncertainty for the success of device manufacturability. Since each generation of low-k dielectric has its own mechanical properties and integration characteristics, IC manufacturers are required to develop CMP and other related processes when migrating from one generation to the next. Tool and process extendibility, manufacturing yield, and device reliability become major concerns because with each new manufacturing node, IC manufacturers must change low-k dielectric materials and processes.
Low-k integration
An alternative to the low-k strategy described above is to leap from conventional oxide (k = 4) to ultralow-k below 2.2. The difficulty and cost of process migration to tighter design rules is substantially reduced by eliminating the costly development of each generation of low-k dielectric and associated process integration issues. Most ultralow-k dielectric materials are porous and the k value can be manipulated by increasing the porosity without changing the actual material and the process tool. However, the ultralow-k dielectrics (k<2.2) used in copper metallization are generally too soft or have insufficient adhesion to survive the stress placed on them by the CMP process.
For example, Figs. 1a and 1b show the rupture of a 0.18µm trench and copper trench delamination from the pure ultralow-k dielectric material. As shown in Fig. 2, the failure model indicates that the mechanical strength of copper trench/wire integrated with pure ultralow-k dielectrics decreases by a factor of three when migrating to the next IC manufacturing node. The extent of decrease in the mechanical strength of the copper trench structure makes CMP nonextendable for future manufacturing nodes.
Redefining low-k selection criteria
The Ultra SFP technology developed by ACM Research is the first to provide the industry with copper/low-k integration capability enabling the direct move from conventional oxide to ultralow-k dielectrics (k<2.2). Because this new chemical polishing process is electric current controlled, it induces no mechanical stress on a copper/low-k structure (k<2.2), as shown in Fig. 1c. These results promise an earlier than anticipated implementation of ultralow-k dielectrics into copper interconnect structures.
 Figure 4. Removal rate nonuniformity of SFP. |
While technical challenges related to the overall strength of multilayer interconnects remain, with respect to the kinds of CMP-induced damage noted previously, SFP means mechanical strength is no longer an issue for low-k dielectric process integration. IC manufacturers can focus on the characteristics of overall dielectric material performance, such as etching, thermal stability, and electrical properties. As a result of Ultra SFP, softer dielectric films like spin-on, porous Xerogel/ Aerogel materials, are now viable candidates for integration in the damascene process. These porous films can be "tunable" and have low-k dielectric ratings of 2.5-1.5 vs. k>3 for many of the current low-k insulators being used in prototype copper processes.
Ultra SFP
The principal of Ultra SFP is electropolishing, a technique that has been used for a variety of metal surface modifications since 1912. Electropolishing results in smooth, bright surfaces with reduced surface stress and increased corrosion resistance. Consumer applications include golf clubs, tools, hardware, vessels, pipes, and tubing. When the technique was applied to polishing copper on a wafer, and the thickness of the copper layer reached a few thousand angstroms, difficulties were encountered in controlling the potential drop from the center of the wafer to its edge [1]. A thickness profile of a copper film polished by conventional electropolishing would show that the thickness of copper at the edge of the wafer (wafer diameter 1.2 in.) is close to zero. The thickness at the center portion of the wafer, however, would be more than 3000Å. The loss of copper on the edge of the wafer means it cannot be polished further, since no current will pass through the center portion of the wafer to the edge where the electrode is located.
 Figure 3. Ultra SFP technology. |
R&D efforts by ACM Research during the last few years were targeted at overcoming the fundamental limitations of electropolishing as described above. The basic approach is to localize polishing current through a patent pending technology (Fig. 3); electrical current is used to remove copper in a controlled polishing process. The system locally controls the current, dividing the wafer into zones that are polished in sequence. The center portion of the wafer is polished first, then the polishing process proceeds from the center to the next zone, and the next, and so on, until the edge of the wafer is reached. In this manner, the polishing current can be conducted to the electrode located at the edge of the wafer. Through precise power supply control, this unique electropolishing process allows for the removal of copper at the atomic layer level.
The removal rate of copper using the localized polishing method is proportional to the current density. The greater the current density, the greater the removal rate. A complete control of polishing rate from the center to the edge of the wafer during the entire polishing process has been demonstrated, as shown in Fig. 4. A thickness removal within wafer nonuniformity (WIWNU) of 0.8-1.2% (1s) has been achieved using this procedure and the corresponding thickness removal wafer-to-wafer nonuniformity (WTWNU) was 0.59% (1s).
Because only the copper is removed during the Ultra SFP process, no dielectric loss or erosion has been observed using the technique. This benefit will significantly improve the global planarity of the interconnect layer as the number of stacked interconnect layers increases, particularly for most logic devices (CPUs, ASICs, FPGAs [field programmable gate arrays] and PLDs [programmable logic devices]), which may have up to ten layers in the future. Yield loss caused by errors of defocus in the lithography step will be minimized, regardless of the number of stacked interconnect layers, as long as the dielectric is laid down uniformly. Excellent WIWNU has been demonstrated for both spin-on low-k and ultralow-k.
Because the SFP system provides precise control over copper removal, there is virtually no dishing (Fig. 5). No erosion was found at the high-pattern-density area. One can precisely control the amount of copper removal and total recess according to the design rule. Figure 5 also illustrates polished surface morphology with 7000Å removals as measured by atomic force microscope (AFM). The root-mean-square (RMS) of surface roughness is 19Å.
There are several common barrier materials (Ta, TaN, Ti, TiN) that are being used for copper processing, all more inert than copper. Therefore, when these materials are used, electropolishing is not feasible without compromising copper removal. One can remove the barrier layer using either wet chemical etch or dry plasma etch [2]. The selectivity of TaN to oxide is as high as 20, and the selectivity of barrier Ta to oxide is as high as 18. The etch rate for copper is negligible and no corrosion on the copper surface was observed after the plasma-etching process.
Figure 6 shows Ultra SFP as a stand-alone, single-wafer processing system. In-house evaluation showed a throughput of 30 wafers/hr using multiple stacked modules accessed by dual robot end-effectors. The Ultra SFP system incorporates three polishing modules and three cleaning modules, including bevel and backside cleaning. The use of multiple stacked modules reduces the stem footprint (6 ftx10 ftx8 ft) — it's almost one-half the size of a typical CMP tool. The system's automated features are in compliance with Semi standards for safety and automation. Automation features include in situ remove rate uniformity monitoring and control, and endpoint detection for the entire wafer. The NT-based software and control system can be accessed easily for remote diagnostics.
By eliminating consumables such as pads and slurries, Ultra SFP achieves a substantially lower cost/wafer than conventional CMP processing tools. Cost of ownership is enhanced by the system's small footprint, which remains the same for both 200 and 300mm tools. Because Ultra SFP eliminates or significantly reduces CMP process-induced defects such as erosion, delamination, dielectric loss, lithography defocusing, and scratches, capital productivity is improved.
Conclusion
A new technology has been developed to remove copper by using a stress-free process based on electropolishing copper without dielectric loss, erosion, or delamination. No delamination was observed during processing using oxide, low-k (k = 2.8), and pure ultralow-k dielectrics (k<2.2). Polishing rates WIWNU of 0.8% and WTWNU of 0.59% for 200mm wafers were achieved.
Acknowledgments
Ultra SFP is a trademark of ACM Research Inc.
References
- R.J. Contolini, A.F. Bernhardt, S.T. Mayer, J. Electrochem. Soc., 141, 2503, 1994.
- S. Kondo, N. Sakuma, Y. Homma, Y. Goto, IITC, p. 253, 2000.
David Wang received his BS from Tsinhua University in China, and his MS and PhD in semiconductor processing and equipment from Osaka University, Japan. He was manager of the R&D program at Quester Technology Inc. before the formation of ACM Research. Wang is president and CEO of ACM Research Inc., 46520 Fremont Blvd., Ste. 610, Fremont, CA 94538; ph 510/445-3700, fax 510/445-3708.
Stephen Sun Chiao is professor of electrical engineering at San Jose State University and director of its High Frequency Electronics Lab. He is a member of ACM Research's technical advisory board.
Mohammed Afnan was a system architect for CVD systems and managed 300mm-product software development at Quester Technology before ACM Research was formed. He is director of the Business Unit at ACM Research.
Paul P.H. Yih has been on the technical staff at AT&T Bell Labs' Display Research Department and at Lucent Technologies in the VLSI Technology Department of Bell Labs. He is process integration and applications manager at ACM Research.
Michel Rehayem has served in various sales and marketing posts at CVC Products, Sensarray Corp., General Signal Thin Film, ASM America, Tempress, and Bruce Systems/BTU Engineering. He was director of sales and marketing for Quester Technology before the formation of ACM Research, where he is now director of sales.