Challenge for the new millennium: Managing mask costs
10/01/2001
Kenneth A. Rygler DuPont Photomasks Inc.
There has been growing concern over the so-called million-dollar mask set. While the cost of producing advanced photomasks continues to increase, they remain the lowest-cost approach to staying on pace with Moore's Law. Though some say that the move deeper into the subwavelength era will see a sharp rise in mask costs, management strategies can mitigate these costs.
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Application-specific integrated circuits (ASICs) power much of today's electronic equipment. Semiconductor manufacturers want to capitalize on their intellectual property (IP) through the development of unique products, many of which are ASICs. Non-recurring engineering (NRE) charges, which include the cost of masks, must be managed in a way to allow the continued proliferation of ASICs. Otherwise, chips will migrate from application-specific to standard to commodity products. The result is a production game more easily won by those with the lowest production costs and access to the most capital — not necessarily those with the best ideas.
While the cost of masks for standard products such as microprocessors and DRAMs can be amortized over long wafer runs, ASICs are usually produced in smaller wafer lots. Clearly, on the basis of number of runs/mask, ASICs become more expensive to produce as mask prices increase. But consider this: as a percentage of NRE costs, mask costs for ASICs may actually be the same or lower than they were five to 10 years ago. Feature sizes of 0.18µm and below allow a single system-on-a-chip (SOC) to have the same functionality as multiple chips found in older electronic systems. To the extent that many of these chips were ASICs, each of those individual chips required a mask set with its own NRE, as well as complex multilayer boards and other interconnects. If one compares the photomask costs and associated NRE charges for producing the same functionality in a single chip vs. multiple chips, today's more complex photomasks deliver far more bang for the buck than they did 10 years ago.
But beyond increased value per mask, there are strategies that can effectively reduce mask costs. A primary one is the growth in collaboration among chip designers, their EDA tool suppliers, and photomask manufacturers earlier in the image-creation process. Eliminated is the "trial and error" of mask design and the accompanying cost in time and materials. This will also help to ensure that designs are more photomask- and lithography-friendly and that they are more cost-effective to produce.
New strategies in prototyping and low-volume wafer runs can also reduce costs. For example, DuPont Photomasks is working with both integrated device manufacturers (IDMs) and foundry customers on multiproduct wafers, allowing several devices to be contained on a single reticle set. Other chipmakers are utilizing smaller fields for prototypes and low-volume runs, trading lower reticle costs for some reduction in stepper throughput. With the current low capacity utilization in many fabs, this may be an attractive route.
For photomask producers, inspection strategies that eliminate redundant inspections and focus on detecting and repairing only printable defects can reduce the cost of maskmaking. Accepting reticles with defects that have no effect on device performance or wafer yield is a cost saver, in time and money.
Overall, mask prices will come down from their introductory-level prices. At each technology node, prices tend to be very high, as tools designed for older photomask technology are extended to build prototypes. As volumes grow, however, yields improve and advanced tools and processes are introduced, and improved productivity and yields lead to price reductions. So while initial 0.13µm photomask sets may have approached $1 million, this price is expected to decline.
Other opportunities exist to reduce substantially the costs of producing subwavelength reticles. For example, we are creating special photomask sets for chipmakers in the high-wafer-volume, high-performance segment (e.g., DRAMS, microprocessors), medium-wafer volumes (SOC, FPGA, DSP, ASSP), and low-wafer volumes (ASIC). The key to these offerings is the degree to which we implement lower-cost, high-performance, laser-based processes as opposed to more expensive electron beam processes.
Optical lithography will continue to extend the semiconductor industry's capabilities beyond the limits we see today, as it provides the lowest-cost, lowest-risk path to achieving the semiconductor mantra of the last 50 years: smaller, faster, cheaper. To do this will require unprecedented cooperation between design, photomask, and lithography companies, which can also enable the small wafer volume applications to continue to thrive.
Kenneth A. Rygler received his bachelor's degree in chemistry from Bethany College and has attended AMA and the Executive Management School of Pennsylvania State University. He is executive VP of Worldwide Marketing & Strategic Planning at DuPont Photomasks Inc. and a member of the board of directors of DuPont Dai Nippon Engineering and DuPont Photomasks Taiwan Ltd.