Optimal insertion points for OPC and PSM in design flows
09/01/2001
LITHOGRAPHY SPECIAL REPORT: MASKS
Frank Schellenberg, Mentor Graphics, San Jose, California
overview
To reexamine the optimal insertion points for OPC and PSM, pattern data are manipulated and presented both in the context of the litho/design flows and as a set of transformations between discrete states. Although OPC retains its insertion point at layout verification, PSM represents a more complicated situation.
The communication between IC designers and manufacturers, although essential for the production of working devices, is often done at arm's length. In foundries, the business model is concentrated on manufacturing expertise, while design expertise is the focus of their fabless customers, thus helping drive communication toward the minimum necessary information. This is usually embodied in a set of concrete design rules, which represent the physical dimensions that a manufacturer can guarantee.
There are some emerging technologies, however, where a greater degree of communication is required. This is especially true for lithography technology, where the design information is converted layer by layer to a physical layout on reticles and used to manufacture the actual circuit patterns.
Resolution enhancement technologies
For decades now, the physical phenomena of optical systems used for lithography, particularly diffraction and phase interference, have been well understood and reticle layouts compensated in anticipation of these effects [1, 2]. Pre-compensation of the reticle can dramatically improve image contrast and pattern fidelity, extending the limit of the minimum feature and pitch that can be resolved. The general name for this field is resolution enhancement technologies (RET).
 Figure 1. The downstream portion of the litho/design flow can be illustrated as a series of "states" or deliverables, connected by a series of transformations. |
One of the two main RET approaches is optical and process correction (OPC), sometimes called optical proximity correction, in which the apertures of the reticle are adjusted to add or subtract the necessary light to increase pattern fidelity. The second main RET approach is phase-shift masks (PSM), in which topographic structures are created on the reticle to introduce contrast-enhancing interference fringes in the image.
These represent independent controls of two fundamental properties of the optical wave passing through the reticle: amplitude (using OPC) and phase (using PSM). Both require that the polygons used to define the reticle openings be changed, therefore significantly interacting with the design.
Two other independent variables of the optical wave — propagation direction and polarization — also exist. Propagation direction is controlled in a widely used RET called off-axis illumination (OAI). However, OAI generally provides global processing effects not specific to local polygon environments, and polarization is currently little used in RET. Therefore, neither are discussed at length in this paper.
 Figure 3. Each "state" of Fig. 1 has its own verification step. |
Although not new ideas, both OPC and PSM are now becoming widely used through automated software that manipulates layout polygons. Whenever designed polygons are changed, however, the impact on the design must be known and evaluated. Since these polygon manipulations are very similar to other routine IC design procedures, it would be natural for electronic design automation (EDA) software to execute these steps. Correct execution, however, requires some detailed knowledge of the lithography details, which most IC designers do not possess or care to possess.
Litho/design workshops
In the mid 1990s, several Sematech workshops were held to address the relationship of design flows to OPC and PSM software. At these workshops, individuals from the EDA, mask, and lithography communities participated in discussions focused specifically on the relationship of the new lithography technologies to design [3]. A key result of the workshops was a set of process flows. Participants from each specialty presented a sequence of steps typically executed in manufacturing (see figure at right). Although many design, mask, and lithography processes may vary significantly from this template, this flow provides a basis for discussing the impact of these technologies.
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Subsequent litho/design workshops addressed the impact of the adoption of OPC and strong PSM technologies (also called Levenson, or alternating shifters) on this flow. Key topics of discussion were suitable insertion points for the technology and the impact on subsequent process steps. For OPC, insertion was considered most suitable at the layout verification step, along with design rules checking (DRC) and before tape out. This insertion point was primarily selected to ensure that the layout generated up to this point, typically after logic and timing tests, would not be corrupted or degraded by the alteration of the layout polygons. Also significant was the addition of an "OPC DRC" step following the OPC step, to verify the absence of corruption.
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Figure 2. The litho/design flows produced by the Sematech Litho/Design Workshops represent a sequence of steps typically executed in manufacturing.
For PSM, although the strongest impact was on the mask-manufacturing steps, the place and route (P&R) step was generally agreed to be the most suitable point of insertion for design manipulations. Therefore, smaller pitches made possible through PSM could be "designed in" when the lines are initially created, rather than generated after the fact with a compactor tool. For both OPC and PSM, insertion after tape out, and during the "data massaging" step in the mask shop, was rejected as a suitable point of insertion. The main objection was based on trust — a design at this point typically had millions of dollars invested in terms of engineering time, testing, and verification. One estimate put the "investment" at over $40 million. The risk, without the ability to check alterations through some form of verification tool, was viewed as highly undesirable.
Litho/design flows as state transitions
Examination of litho/design flows leads to an interesting observation. Though typical of a sequence of steps executed to produce integrated circuits, they also represent individual jobs or tasks. Thus, another way to structure the process flow is to view it as the creation of a sequence of discrete states, with various EDA tools or other software products being used to create transformations from one state to another. A state approach to the last portion of the litho/design flow is shown in Figure 1 on p. 63. In this view, the "states" correspond to discrete deliverables that commonly represent the items bought and sold by different organizations. For example, the discrete states are the netlist, the layout, the reticle, and the chip on the wafer itself. Actions on states serve to execute a series of transformations: P&R serves to transform a netlist into a layout; mask writing transforms a layout into a reticle; lithography and processing transform a reticle set into a working IC.
Another observation is that each of these states requires an independent verification step before the deliverable is passed on to the next step (Fig. 3). Although the verification steps are quite different from each other, passing verification with an objective verification tool is critical for the flow to continue.
Insertion points for OPC and PSM
The state approach makes it clear that verification must consist of not only self-consistency checks, such as DRC for layouts, but also checks between states. In this context, layout vs. source (LVS) for layouts represents an upstream check, looking back to the last state, the netlist (Fig. 4). Using this approach to reexamine the insertion points for OPC and PSM, the introduction of the "OPC DRC" step (more commonly called ORC, optical rules check) ensures that OPC changes are actually manufacturable, a "downstream-looking" step for layout verification. This compliments the "upstream-looking" step of LVS and the self-consistency check of DRC (Fig. 5), adding symmetry to the verification step.
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Figure 4. Using the state approach, physical verification for the IC layout relies on self-consistency checks as well as consistency between states.
Where does OPC itself fit in? In the traditional context of reticles, after verification (at inspection), any detected errors (defects) are corrected (repaired). At this point, after layout verification, the parallel step is to "repair" the layout until it becomes manufacturable, using a layout correction mechanism. OPC is just such a correction mechanism (see Figure 5). The result is a natural insertion point for OPC at layout verification, an approach that has proven commercially successful [4].
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Figure 5. ORC (silicon vs. layout check) adds a downstream view, balancing layout verification. OPC is inserted in the verification flow when a layout fails manufacturability checks.
Phase shift mask presents a more complicated picture. Commitment of phase assignment for features at the P&R step, as the workshops suggested, leads to some unforeseen consequences.
Most notably, from a practical point of view, there is still no reticle inspection and repair technique that guarantees defect-free phase-shift reticles. Furthermore, making large phase-shift regions (etching into the quartz reticle) can further introduce defects. It is therefore desirable to minimize the area of the reticle actually etched. Phase assignments should be made with that metric in mind.
Yet, if the assignment to form a phase-shifted region is made at the P&R step as each structure is formed, the software has no way of knowing which assignment will eventually have the largest area. The final area assigned to be shifted may become far larger than is optimal, suggesting it is best to actually make phase assignment at the last possible moment, possibly at the step of fracturing the data for mask writing. However, phase shifting alone does not generally deliver the expected lithographic performance. This is because the process distortions that OPC commonly correct are also created during PSM processing. Best results are therefore achieved only if OPC is added after phase shifting, to compensate for both amplitude and phase effects [5]. For this reason, the PSM insertion must occur before the final OPC and verification steps.
 Figure 7. ORC simulations with (blue) and without (red) OPC illustrate its effectiveness. |
The final compromise is that the insertion of PSM is also optimal at the verification step, as yet another step to "repair" a design that has not passed a manufacturability check. In this case, only the minimum area is phase-shifted, and the phase shifting is applied together with OPC in an optimal manner. The example shown in Figs. 6 and 7 (see below and on p. 74) illustrates a portion of a SRAM chip with the layout and verification results on the left and a SEM micrograph of the final etched wafer on the right. Here, the beneficial interference effects of the phase shifting have been realized, and microprocessors fabricated by this technique have proved significantly faster. On the other hand, the line-end pullback — characteristic of the process at these dimensions — has been compensated by the judicious use of OPC. Software, such as the Calibre suite of products, contain a classic DRC tool, as well as OPC and phase-shifting capabilities tailored specifically for the problem of making small gates [5]. The integration of both the OPC and PSM into the layout verification step achieves the optimal insertion point identified for OPC by the litho/ design flow, as well as a compromise between the early insertion of PSM at the P&R step, and manufacturability problems that can occur downstream.
Conclusion
In this paper, we have reported the litho/design flows for the insertion of OPC and PSM into existing manufacturing process flows, and reinterpreted this as a set of transformations between states. This new interpretation provides a format to reexamine the optimal insertion points for OPC and PSM. Although OPC retains its insertion point at layout verification, PSM is not as straightforward, with PSM-compliant design rules being followed at the P&R step, though actual phase assignments are more optimally placed at the layout verification step as well.
Acknowledgments
The author would like to thank Marc Levenson for first introducing him to the phase-shifting problem; Andrew Kahng for originally suggesting the "state transformation" interpretation of the litho/design results; Chris Spence for sharing his recent work on the practical application of phase shifting and OPC to microprocessors; and Pat LaCour, Mentor Graphics, and Andrew Moore, TSMC, for many helpful discussions.
References
- M.D. Levenson, N.S. Viswanathan, R.A. Simpson, "Improving Resolution in Lithography with a Phase-Shifting Mask," IEEE Trans. Electron Devices, ED-29, pp. 1828-1836, 1982.
- B.E.A. Saleh, S. Sayegh, "Reduction of Errors of Microphotographic Reproductions by Optimal Corrections of Original Masks," Opt. Eng. 20, 1981, p. 781.
- F.M. Schellenberg, "Design for Manufacturing in the Semiconductor Industry: The Litho/Design Workshops," in Proceedings of the 12th International Conference on VLSI Design, pp. 111-119, ed. R. Sipple, IEEE Computer Society Press, Los Alamitos, CA, 1999.
- F.M. Schellenberg, P. LaCour, "Implementation Issues for Production OPC," in Photomask and X-Ray Mask Technology VI, ed. H. Morimoto, pp. 249-258, Proc. SPIE 3748, 1999.
- C. Spence, M. Plat, E. Sahouria, N. Cobb, F. Schellenberg, "Integration of Optical Proximity Correction Strategies in Strong Phase Shifter Design for Poly-Gate Layer," in 19th Annual Symposium on Photomask Technology, pp. 277-287, ed. F. Abboud, B. Grenon, Proc. SPIE 3873, 1999.
Frank Schellenberg received his PhD from Stanford University in applied physics. He turned to lithography research in 1990, and holds patents on phase-shifting and OPC technology. He has worked at IBM Almaden Research Labs, HP Labs, and Sematech. While at Sematech, he sponsored several software start-ups in the area of OPC technology. In 1998, he joined Mentor Graphics, 8005 S.W. Boeckman Rd., Wilsonville, OR 97070; ph 408/436-1500, [email protected].