Tuning the process flow to optimize copper CMP
09/01/2001
Konstantin Smekalin, Robin Cheung, Dana Tribula Applied Materials, Santa Clara, California
overview
CMP is considered the biggest process challenge for the new generation of copper-based chips. Problems that arise here ultimately affect chip performance. However, chip manufacturers can significantly improve results by optimizing pre- and post-CMP steps. This article looks at copper CMP in the context of the entire interconnect process flow, examining steps that can be taken to make CMP easier in next-generation device processing.
 Figure 1. A typical PVD TaN barrier layer is shown with a thickness of ~250? on the top surface. |
At the 0.13µm node and beyond, the copper dual damascene architecture will join the current subtractive aluminum architecture for IC interconnects as a mainstream architecture; and the impact on overall chip performance will be greater. To ensure optimum device performance, yield and cost effectiveness, bottlenecks related to the copper CMP process must be minimized. The solution is a move to greater integration of processing steps.
The best way to overcome "CMP problems," which often result from features carried over from previous process steps, is to look at CMP in the context of the entire metallization sequence. CMP is the last step in the damascene sequence, and creates the topography on which subsequent layers are built. The impact of CMP topography increases with each subsequent layer, affecting capping dielectrics, interlayer dielectric deposition, lithography and etch steps, post-etch cleaning barrier/seed, and ECP copper deposition.
Performance impact
Typically, in copper dual damascene processing the interconnect vias and the lines in a single metal deposition step are first filled with copper. The copper lines are then defined when the field copper is polished down to the oxide dielectric. Ideally, all the copper from the field regions must be removed without affecting the copper in the trenches.
Erosion of the oxide or dishing in the copper that occurs during the CMP process reduces the thickness of the interconnect lines, causing increased RC constant and circuit delays.
Optimizing all interconnect processes to ensure that dishing, erosion, and defect levels are not exacerbated is critical to chip performance. Internal studies have shown that improved within-wafer nonuniformity of the as-deposited copper film results in a simpler and lower-cost CMP process.
Design considerations
The ideal place to start when attacking the dishing and erosion problem is at the very beginning, during chip design. Dishing and erosion systematically increase as a function of feature size and feature metal density. CMP difficulties are increased when there are extreme variations in feature density across the die. These variations affect array topography and the range of within-die metal thickness. Therefore, designers generally take into consideration the impact of layout pattern, pitch, and density on manufacturability. Essentially, the goal is to distribute features as evenly as possible across the chip surface while maintaining the feature density at levels of 40-60% within a planarization length, the distance over which the pattern density gets averaged by CMP, typically 1-3mm.
The following examples of optimized die and wafer layout have proven successful and have found wide acceptance.
- Step-to-edge approach: Partial die are printed at the wafer's edge to minimize or eliminate the effect of the transition from flat dielectric to patterned area.
- Dielectric dummy fill approach: Wide metal lines, both within the die and in the wide "streets" between the die, are supported with embedded pillars of dielectric.
- Metal dummy fill approach: Dummy metal features are created in the dielectric to increase the uniformity of a densely patterned circuit [1].
Ultimately, a design with the least variation in density and pitch and the greatest degree of homogeneity in pattern layout will encounter the fewest CMP-related dishing and erosion problems. While ECAD tools can address this, the reality of design constraints and/or development time in the face of enormous product diversity often means that homogeneous patterning is ignored. In any case, the next step is to look at the interconnect process flow.
Optimizing barrier/seed processes
The barrier and copper seed layers provide the critical surface conditions for void-free gap-fill ECP. The barrier layer prevents copper diffusing into the dielectric insulator between the copper lines and improves adhesion between metal stack and dielectric layers. The seed layer provides an electrical path to enable the ECP fill. The interfaces between the barrier and dielectric, and between the barrier and seed, play a key role in device reliability. Cu morphology and defect problems may begin during these processes.
Two main barrier materials are currently being used, Ta and TaN (Fig. 1); others are being investigated. Ultimately, the CMP process needs to take into account the barrier type and thickness. If the barrier layer is used as a polish stop-layer for the copper removal step, slurry selectivity between copper and the barrier is critical. The International Technology Roadmap for Semiconductors, 2000 Edition, Interconnect Roadmap calls for progressive thinning of the barrier layer, making selectivity an even more delicate balance, requiring higher selectivities. Current commercially available slurries have selectivity of copper to Ta or TaN in the range of a few dozen to a few hundreds. A new generation of copper consumables will be required to bring the selectivity into the thousands range to ensure that overpolishing of copper layer nonuniformity will not bring about the complete removal of thin barrier film in exposed areas. Even if high selectivity is achieved, good within-wafer uniformity of the copper bulk removal step remains a must, as the ever-thinning barrier will not sustain the prolonged overpolish called for by nonuniform copper removal.
How ECP affects CMP
Electrochemical plating (ECP) seems to be the most viable deposition technique for advanced copper-based metallization, but the plating process can cause wafer-scale, die-scale and feature-scale metal thickness nonuniformities that result in post-CMP variations in metal and dielectric films. Ideally, pre-CMP processes should yield minimal as-plated topography on individual features and associated array-scale dimensions (Fig. 2). These concerns begin at layout pattern and continue at ECP, where the primary factors to control are overplating, edge-bead removal, and anneal. For example, overplating, which results from bottom-up superfill, can be controlled with ECP hardware and chemistry. Optimal post-CMP topography is achieved if overplating over dense metal arrays after ECP does not exceed a few thousand angstroms.
While the goal is certainly to minimize overplating, equally important is that the plating profile be consistent from wafer to wafer. Center-to-edge profiles can be changed in the ECP process. To yield the best post-CMP results, the wafers coming from ECP into CMP need to look as much alike as possible. During ECP, therefore, center-to-edge profiles should be consistent so that post-CMP profiles of the remaining metal are also consistent. Figure 3 shows run-to-run repeatability of the electrical parameters of post-CMP wafers, which reflects the post-CMP copper line-thickness stability. Standard deviation within wafers is less than 3%, and wafer-to-wafer is even less — about 2%. With consistent wafer-to-wafer ECP film thickness, the result is consistent line resistivity after CMP.
While the ECP film can also exhibit nonuniformity across the wafer and CMP can potentially accommodate such nonuniformity by varying the removal rate across the wafer, there are limits to what is practical, feasible, and efficient.
 Figure 3. Run-to-run repeatability of an ECP process helps achieve run-to-run repeatability of electrical parameters of post-CMP wafers. |
Wafer edge engineering is another ECP issue that can have a major impact on CMP [2]. It is essential to keep the wafer edges free of loose copper that can flake off and cause scratches during CMP. Finally, ECP films need to be annealed so that consistent CMP removal rates can be maintained [3], and pit defects are not introduced or revealed during CMP. A pre-CMP anneal, which addresses this problem, lowers resistivity and stabilizes the microstructure for consistent CMP removal and increased device reliability. The anneal process conditions affect copper grain size distribution, however, and therefore affect the frequency of pit-type defects that are possibly the result of grain pull-outs during CMP. Abnormally large grains with weak grain boundary interfaces may be especially prone to pullouts. Varying pre-CMP anneal conditions can greatly affect the grain distribution and reduce the number of pit-type defects that are only visible after CMP (Fig. 4).
Optimal CMP
Clearly, the CMP process must result in very low topography. Topography is additive. At every step, topography problems worsen with each additional layer, and excessive topography may necessitate intermediate dielectric CMP, adding cost and complication to the process. It may even require massive overpolish of copper residues on the next metal layer, a solution that will cease to work after metal two or three. Optimal CMP minimizes topography, dishing, metal residues, and corrosion. There are several ways to control topography that can be used at different levels. The goal is to minimize over-polishing. For example:
- A highly selective approach with wide overpolish margin tries to remove copper only from the field, preserving line thickness, and stopping "dead" on barrier.
- A nonselective approach removes bulk copper, possibly leaving some copper residue. In the subsequent barrier removal step, the goal is to remove residual copper, all the barrier, and some dielectric at similar rates.
Dishing in the copper lines arises during the over-polish required to remove the remaining field copper film [4]. It begins as soon as the barrier begins to clear. A solution is to monitor the clearing of copper in various areas of the wafer simultaneously and independently. To address this, CMP vendors have introduced various endpoint detection techniques with different degrees of spatial resolution.
Metal residue, which can cause shorts between copper lines, can also be controlled by process and endpoint optimization. The key is to ensure that the copper is indeed cleared from the entire wafer surface, not just from the localized area used for endpoint monitoring. In general, it is important to look for ways to ensure highly uniform polishing conditions. Nonuniform conditions can cause excessive erosion of the dielectric oxide as polishing clears the remaining copper. That is why it is important that the CMP tool deliver low, uniform pressure across the wafer during polishing.
Corrosion of the copper surface can be avoided by applying passivating solutions to the wafer surface any time there is an interruption to the polish process, whether it be intentional (as during wafer transfer) or unintentional (such as a tool breakdown) [5, 6]. Scratches on the wafer surface can be avoided by appropriate selection of abrasives used in the slurry, especially in the slurry used for final clearing of the barrier. Slurry filtration can also help eliminate particles that might cause micro-scratching of copper and oxide surfaces [7]. During post-CMP cleaning, a megasonic clean followed by a brush scrub, nonmetallic residue can be removed from the wafer surface [8]. In the end, the wafer must be clean, dry and free of particles. The quality of the first step in the next cycle — a high-temperature deposition step — is seriously compromised if residue is left behind.
Integrated equipment sets
Chipmakers are finding advantages in getting partially or fully pre-integrated equipment sets for their copper damascene devices. This can help reduce development time of the full process flow.
Two or more technologies may operate in sequence, such as dielectric deposition, dielectric etch, barrier/seed deposition copper bulk fill, and CMP for the damascene copper process.
Adding to this concept is the more complex issue of integrated feed forward/feedback inspection and metrology made possible by advanced process control (APC) software. Systems in an equipment module can use APC to automatically control their operation between steps for optimum technical and economic results. This approach becomes particularly valuable as the complexity of backend integration increases.
 Figure 4. The progressive reduction (from right to left) of post-CMP pit-type defects based on optimization of pre-CMP anneal conditions is demonstrated. |
One example is the copper ECP/CMP interaction. Traditionally, the main ECP challenge was filling ever-shrinking high aspect ratio via/trench combinations. In pursuing this goal, ECP developed best known methods (BKM) with very impressive filling results, but used process/chemistries that ultimately compromised global topography on the wafer and hindered CMP efforts to achieve excellent post-CMP topography. In a similar way, the copper CMP process can resort to using chemistries to protect the copper surface from corrosion, which in turn can compromise the subsequent CVD dielectric deposition for the next interconnect level.
Closed-loop process control is most beneficial to the ECP and CMP processes, which are at the end of the metallization sequence. Post-ECP film thickness and uniformity measurement can feed information back to the ECP system to adjust its deposition parameters for optimum polishing, including both polishing results on the wafer and polishing system efficiency. Then, using thickness and uniformity information fed forward from the ECP step, the CMP system can adapt its initial polishing step to meet those conditions and further adjust secondary or final polishing steps according to information gathered between platens. Final metrology and defect data can be used to determine the status of wafers before going on to the next metallization level.
Beyond stand-alone systems, inspection and metrology tools are already being integrated directly onto the various systems in the process sequence where they can operate with little or no impact on system throughput. APC software to connect systems in feedback and feed forward control loops is also becoming available. In the future, little operator intervention may be needed for long periods of operation.
Future considerations
Copper CMP has introduced a whole new set of challenges that are still being addressed. For the most part, they center on process controls, but CMP consumables need to be continuously optimized to meet new challenges from ever-shrinking geometries and the introduction of new, low-k dielectric materials. In particular, CMP development needs to address the challenges of new polymer and porous low-k materials; new materials may demand new process steps. It is widely anticipated that materials with dielectric constants below 2.0 will have a significant pore volume and lower modulus that will not be able to withstand shear stresses common for oxide or metal CMP applications of today. As a result, ultralow or zero shear planarization will be required for compatibility with a new class of low-k materials.
Clearly, issues of dishing, erosion, overplating and overpolish indicate that the CMP process needs to be monitored more closely. To do this, CMP tools must gather more information in situ, monitoring the evolution of the copper film with respect to thickness and topography during the CMP process.
Closed loop control, which can help the CMP process compensate for variations in the as-plated wafer, is gaining wider acceptance. The migration toward "smart tools" in all processes will reduce scrap and downtime by eliminating monitor wafers and unnecessary scheduled preventive maintenance. Currently there remains too much process variation between mask sets, increasing the challenges for ECP and CMP at current geometries. The advent of smart tools will help eliminate mask set optimization, saving time and resources.
Slurries will evolve as well, with the increasing role of abrasive-free CMP. Abrasive-free slurries are currently more expensive than traditional abrasive slurries, primarily because of their perceived performance advantage. As their role increases, however, costs should fall to more acceptable levels.
The move to smaller geometries will introduce more complex challenges such as controlling particle size distribution for abrasive slurries and controlling chemical composition for abrasive-free slurries. Environmental issues will continue to demand new solutions as well. Some CMP tool vendors are working on techniques to reduce the amount of copper-bearing affluent, which may ultimately involve both process and hardware modifications.
Conclusion
CMP processes must be viewed in the context of the previous — and subsequent — processing steps. Optimizing each step in the interconnect process flow for CMP will ultimately reduce the CMP challenge. Dramatic improvements in yield and throughput can be expected when the optimization data from each step are fully integrated in feed-forward and feed-backward process control.
References
- J. Tony Pan, Ping Li, "Copper CMP and Effect of Dummy Structures," Applied Materials, Proceedings of 2000 VMIC.
- Kenneth R. Harris, Boon Yong Ang, "Yield Implications of Wafer Edge Engineering," AMD, Proceedings of SPIE, Vol. 4229, 2000.
- K. Smekalin, Q.T. Jiang, "Impact of Low-Temperature Anneals of Electroplated Copper Films on Copper CMP Removal Rates," National Semiconductor, MRS 1999 Spring Meeting, Symposium P, San Francisco, Materials Research Society 1999.
- J. Tony Pan, et al., "Copper CMP and Process Control," Applied Materials, Proceedings of 1999 Chemical-Mechanical Planarization-MIC, Feb. 1999.
- I. Dugdale, J.B. Cotton, Corros Sci., 3, 69, 1963.
- Carlyn Sainio, "Corrosion Control during Cu CMP," Intel Corp, 2000.
- Geanne Vasilopoulos, Zhenwu Lin, Budge Johl, and Somit Joshi, Basab Chatterjee, "Copper CMP Defect Reduction Using POU Filtration," Semicon West Technical Program, July 2000.
- Duane S. Boning, Dennis Ouma, James E. Chung, "Extraction of Planarization Length and Response Function in Chemical-Mechanical Polishing," Materials Research Society Spring Meeting 1998, Symposium Q, San Francisco, MRS 1998. For more information, contact Konstantin Smekalin, Applied Materials, 3050 Bowers Ave., Santa Clara, CA 95054; [email protected].